Study of Layout-Effect in CMOS RF Circuit Based on S-Parameter Extracted by

Abstract

As on-chip circuits have scaled into the deep submicron regime, electromagnetic-based analysis has been required for high-speed, high-performance integrated circuit (IC) design. Thus, to solve the effect of parasitic component in layout of CMOS RF IC becomes the most important step to improve the on-chip quality. In this thesis, a simple approach to verify the layout-effect of RF passive and active circuit is based on S-parameter extracted by full-wave EM simulation.