A Study of interconnect effects based on S parameter for CMOS RF IC

Abstract

As the CMOS process technology has developed, the integrated circuits (IC) on CMOS process have become more complicated and compact. As a result, many interactions of components and paths appear in the CMOS chip, even the interactions cause fatal failures of performance in RF IC circuit. Therefore, the analysis of interconnect effects of layout on CMOS process has become a popular topic recently. This paper presents study and analysis of interconnects based on scattering parameter models extracted by full-wave electromagnetic simulation in a CMOS process. This analysis provides well-understanding how coupling affects circuit performance. The analysis of effect of interconnects is investigated in a cascode low-noise circuits (LNA) for 1.84GHz to 2.5GHz. In addition, this paper gives us some ideas of how to make s parameter models for terminals of elements.