PARALLEL TEST METHOD FOR NOC-BASED SOCS

Abstract

Reusing on-chip functional interconnects as test access mechanism (TAM) appeared usual these days. One of the most important functional interconnects for highly crowded future system-on-chips (SoCs) is network-on-chip (NoC). Several NoC architectures including their components like routers and network interfaces (NI) have been proposed for providing better and better services. They allow narrowcast and multicast of packets, in-order packet delivery, guaranteed throughput and best-effort services. Exploiting the preceding research, we present here a parallel test method and a manipulated scheduling method for NoC-based SoCs, while using NoC as TAM, with the goal of reducing overall test time. The proposed test method is compared with previous works using some of ITC’02 benchmark circuits which showed significant test time reduction, up to 58.17% as compared to the latest work.