다중셀 고장 허용 Content Addressable Memory

Abstract

Multiple cell upsets (MCUs) become more and more problematic as minimum feature size approaches 65 nm. The percentage of MCUs is reported to be significantly higher than that of single cell upsets (SCUs) with 20nm technology. In SRAM and DRAM, MCUs are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code and interleaved data columns. However, column interleaving is not practical in content-addressable memory (CAM). It was previously proposed that Hamming distance based approaches are good for SCUs but are not effective for MCUs. These schemes require a large number of extra parity bits for mitigating MCUs, so they are not a practical solution for CAM devices. A novel error correction code (ECC) scheme is proposed in this paper that will work for ever-increasing MCUs. This work demonstrates that m parity bits are sufficient for up to m-bit MCUs, with an understanding of the physical grouping of MCUs. The results show that the proposed scheme requires 85% fewer parity bits compared to traditional Hamming distance based schemes.