Physical Design Methodology of Three-Dimensional IC based on the Optimization of Through-Silicon-Via (TSV)

Abstract

Due to the increasing delay, power, and financial bottleneck beyond 32nm CMOS technology, semiconductor industry began to actively look for alternative solutions such as through-silicon via (TSV) based 3-dimensional (3D) integration. Despite the gains of TSV-based 3D ICs, TSVs create serious design issues in the overall physical design stage. The TSVs are significant layout obstacles due to their large size compared with logic gates and local wires. The research is needed to investigate the positions and numbers of these large TSVs and their impact on circuit timing and power in the early stages of physical design. The TSV planning challenges in the physical design and the development of optimization techniques for TSV-based 3D IC design are determined and explored through various simulations with new ideas in this dissertation. This research proposes the TSV optimization based physical design methodology of 3D ICs, which is composed of several main algorithms as follows. Power aware floorplan optimization algorithm to minimize the number of power/ground (P/G) TSVs is presented. The ideal power pattern to optimize the P/G TSVs is determined in this step, and consequently it plays important roles as the constraint of flooplan optimization. With optimized floorplan, P/G and clock TSVs planning for estimating the demands of TSVs at early stage of physical design is proposed. The initial position and number of them are investigated, and the demands are estimated. Next, the floorplan re-distribution algorithm to optimize the position of TSVs is proposed. The main purpose of this algorithm is to occupy the empty area for TSV insertion considering the estimated TSV demands. Finally, TSV optimization methodology is proposed to avoid the routing congestion and TSVs connection-failure. The proposed TSV optimization brings the stability of routing nets and minimization of total wirelength. The various simulation results show that the proposed methods are more efficient compared to conventional methods, and the proposed methodology is useful as novel design flows in 3D IC physical design.