A study on carrier transport mechanisms of semiconductor devices with a gate all around structure

Abstract

The logic, DRAM, and flash memory devices with high processing speed and storage density made it possible to process and store the mass information. However, the device performance and fabrication process of these semiconductor devices, which are based on a planar transistor, are approaching the physical and technical limits. In order to overcome the limit of conventional MOSFET, many studies on various structures and process techniques have been investigated. According to the International Technology Roadmap for Semiconductors, the next generation cell structure of logic devices such as CMOS and MPU, DRAM, and 3D NAND flash memory is nanowire-type with a gate all around (GAA) structure. A surrounding gate can provide the best possible electrostatic control of the channel region, so the NWFET is the ultimate device structure in terms of gate controllability and short channel immunity. Many studies on NWFET utilizing a GAA structure fabricated by the top-down and bottom-up methods and 3D NAND flash memory with a GAA structure have been advanced. However, Systematic studies on the carrier transport mechanisms and the electrical characteristics in theses semiconductor devices utilizing a GAA structure are less. This study was performed to theoretically investigate the carrier transport mechanisms and the electrical characteristics in semiconductor devices utilizing a GAA structure to understand the physical phenomena and improve the device performance. In chapter 2, electronic structures of semiconductor quantum nanowires is investigated to understand the physical phenomena and the quantum effect in 1-DEG channel of GAA MOSFET. Strain distributions, carrier distributions, and electronic subband energies for quantum nanowires at several temperatures are numerically calculated by using a FDM with and without taking into account shape-based strain effects. The experimental (E1-HH1) interband transitions for quantum nanowires, as determined from the temperature- and structure- dependent PL spectra, are in reasonable agreement with the theoretical (E1-HH1) transitions. In chapter 3, the dependence of the electrical properties on the diameter of the Si nanowire and on the doping concentrations of the Si bulk and the Si nanowires for the GAA TSNWFETs fabricated by the top-down method is investigated to understand their device characteristics and obtain the device optimization. The electrical characteristics of the GAA TSNWFETs and the FETs without Si nanowires are simulated by using the three-dimensional TCAD simulation tools of Sentaurus and taking into account quantum effects. While the switching and the short-channel immunity characteristics, such as the SS, the current drivability per cross-sectional area, and the DIBL for the TSNWFETs, increase with decreasing nanowire diameter, the threshold voltage and the total on-current for the TSNWFETs decrease, resulting in a deterioration of device performances like the sensing speed and margin. When the off-state leakage current is slightly changed within 1 × 10-13 A, the total on-current of the TSNWFETs with an optimized boron concentration is 23.3 μA and is increased by 37% in comparison with that of the as-fabricated TSNWFETs. The current density, the conduction band edge, and the potential profiles in the TSNWFETs clarify the dominant current paths and carrier transport properties. While the threshold voltage of the TSNWFETs linearly increases with increasing nanowire boron concentration, their SS and the DIBL remain almost constant. In chapter 4, the electrical characteristics of the NWFET with Schottky contacts fabricated by the bottom-up method are investigated by using a circuit simulation. A compact model of the current-voltage relation for the NWFET taking into account dependence of the electrical properties on the diameter and the concentration of the Si nanowire of the NWFET with a metal-semiconductor Schottky contact has been proposed. The I-V characteristics of the NWFET are analytically calculated by using a quantum drift-diffusion current transport model taking into accout an equivalent circuit together with the quantum effect of the Si nanowires and a Schottky model at Schottky barriers. The material parameters dependent on different diameters and concentrations of the Si nanowire were numerically estimated from the physical properties of the Si nanowire. The threshold voltage, the mobility, and the doping density of the Si nanowire and the Schottky barrier height at a metal-Si nanowire heterointerface in the NWFET were estimated by using the theoretical model. The simulated results of the Si NWFET are resonable agreement with those of experimental data within a 5% error. In chapter 5, the electrical properties and optimization trap distribution in the charge trap layer of 3D NAND flash memory devices are investigated to improve the retention characteristics and the device reliabilities of 3D NAND flash memory devices. The programming and retention characteristics for CTF memory devices are theoretically simulated by using the model taking into account Shockley-Reed statistics, the continuity equation, and the Pöisson equation. The simulation results show that the dominant tunneling mechanism during the programming operation in the CTF memory devices is varied from the FN tunneling to the DT processes and from the DT to the modified FN tunneling processes due to the decrease of the electric field generated in the tunneling oxide layer resulting from the increase of the injected carriers in the charge trap layer. The trap distribution in the silicon-nitride layer, which is estimated by using experimental results, is used to clarify the retention characteristics of CTF memory devices. Simulation results show that the retention characteristics in CTF memory devices increase with increasing trap density near and above the Fermi-level in the charge trap layer.|빠른 처리 속도와 큰 저장 능력을 갖는 로직, DRAM 및 플래시 메모리 소자는 현대 사회에서 유통되고 있는 많은 정보들의 처리와 저장을 가능하게 해주었다. 그러나 평면 트랜지스터를 기반으로 한 이들 반도체 소자들의 성능과 제조는 이미 물리적인 기술적인 한계에 도달해 있다. 이런 기존 MOSFET 기반 소자의 한계를 극복하기 위해, 다양한 구조와 공정 기술에 대한 많은 연구가 진행되고 있다. ITRS 연구에 따르면, CMOS 및 MPU와 같은 로직, DRAM, 3차원 낸드 플래시 메모리 소자의 차세대 셀 구조는 게이트 올 어라운드 구조를 갖는 나노와이어 형태이다. 채널을 둘러싸고 있는 게이트는 채널을 형성하기에 가장 좋은 정전기 제어가 가능하기 때문에, NWFET는 단채널 효과를 극복하고 채널을 제어하는데 있어 최고의 소자 구조이다. 이를 바탕으로 한 게이트 올 어라운드 구조를 갖는 바텀-업 및 탑-다운 방식으로 제작한 NWFET와 3차원 낸드 플래시 메모리에 대한 많은 연구가 진행 중이나, 이들 반도체 소자들에서의 전하 전송 메카니즘과 전기적인 특성에 관한 이론적인 연구는 아직 부족하다. 본 연구에서는 게이트 올 어라운드 구조를 갖는 반도체 소자에서 발생하는 물리적인 현상을 이해하고 소자 성능을 향상시키기 위해, 다양한 시뮬레이션 기법과 수치해석을 사용하여 이들 소자의 전하 전송 메카니즘과 전기적인 특성을 이론적으로 연구하였다. 2장에서는 GAA MOSFET의 1차원 채널에서의 물리적인 현상과 양자 효과를 살펴보기 위해 양자 나노와이어의 전자적 구조를 조사하였다. 다양한 온도에 따른 양자 나노와이어의 스트레인 분포, 전하 분포, 전자적 부띠 에너지를 스트레인 효과를 고려하여 FDM 방식의 수치해석으로 계산하였다. 나노와이어의 부띠 천이 에너지 이론치는 온도 의존 PL 스펙트럼으로 얻은 측정치와 잘 일치하였다. 3장에서는 실리콘 나노와이어의 직경과 실리콘 나노와이어 및 벌크의 도핑 농도에 따른 탑-다운 방식으로 제작한 GAA TSNWFET의 전기적인 특성을 양자효과를 고려한 3차원 TCAD 시뮬레이션을 통해 연구하였다. 나노와이어의 직경이 작아짐에 따라, TSNWFET 의 SS, 단위면적당 흐르는 전류량, DIBL과 같은 스위칭 특성 및 단채널 면역 특성은 좋아진 반면에, 총 전류량은 감소하였다. 그 결과, TSNWFET에서 나노와이어의 최적 직경은 10 nm 가량임을 확인할 수 있었다. 실리콘 벌크의 도핑 농도를 최적화함으로써 오프-상태 누설전류를 1 × 10-13 A 이내로 막으면서, 전체 전류량이 기존 소자에 비해 37% 증가한 23.3 μA 만큼 흐르는 TSNWFET 소자를 제안했다. TSNWFET에서의 전류밀도 분포, 전도대역 구조, 포텐셜 분포는 주요 전류 경로와 전하 수송 특성을 분명하게 보여준다. 나노와이어의 boron 도핑농도가 증가함에 따라, TSNWFET의 문턱전압이 선형적으로 증가하고 SS와 DIBL 특성은 변함이 없었다. 하지만, 4 × 10-18 cm-3 이상의 boron 도핑에선 GIDL 현상으로 오프-상태 누설전류가 급격히 증가하기 때문에, 나노와이어의 boron 도핑은 적정량에서 조절하는 것이 좋다. 4장에서는 바텀-업 방식으로 제작한 금속-반도체 쇼트키 접촉을 갖는 NWFET의 전기적인 특성을 회로 시뮬레이션을 통해 연구하였다. NWFET에서의 금속-반도체 쇼트키 접촉과 나노와이어의 직경 및 도핑 농도에 따른 전류-전압 관계의 콤팩트한 모델을 제안하였다. 나노와이어에서 발생하는 양자효과를 고려한 전자 전송 모델과 쇼트키 장벽에서의 쇼트키 모델을 SMARTSPICE에 수치적으로 적용하여 계산하였다. 실리콘 나노와이어의 직경 및 도핑 농도에 의존하는 물질 변수를 실리콘 나노와이어의 물리적인 성질로부터 수치적으로 추출하였다. NWFET에서 실리콘 나노와이어의 문턱전압, 이동도, 도핑 농도와 금속-실리콘 나노와이어의 쇼트키 장벽 높이를 이론적인 모델을 사용하여 예측하였다. 시뮬레이션 결과는 실험치와 5% 이내의 오차로 잘 일치하였다. 5장에서는 3차원 낸드플래시 메모리 소자의 리텐션 시간을 늘리고 신뢰성을 높이기 위해 전하트랩층의 트랩 분포 변화에 따른 CTF 메모리 소자의 전기적인 특성에 대한 시뮬레이션을 수행하였다. CTF 메모리 소자의 프로그램과 리텐션 특성을 Shockley-Reed 통계, 연속 방정식 및 포아송 방정식을 고려한 모델을 사용하여 이론적으로 계산하였다. 계산 결과, 전하트랩층에 주입된 전하의 양이 증가함에 따라 터널링 산화막에 걸리는 전계가 감소하기 때문에, CTF 메모리 소자의 프로그램 동작 시 주요한 터널링 메카니즘은 FN 터널링에서 DT, 그리고 변형된 FN 터널링으로 변경됐다. 단순한 전하트랩층의 트랩분포 대신에, 실험 측정으로부터 추출한 전하트랩층의 트랩분포를 모델링하여 CTF 메모리 소자의 리텐션 특성을 연구하였다. 계산 결과, 전하트랩층의 초기 페르미 레벨 위쪽 근처의 트랩 밀도가 증가할수록 CTF 메모리 소자의 리텐션 시간이 증가하고 신뢰성을 높일 수 있었다.; The logic, DRAM, and flash memory devices with high processing speed and storage density made it possible to process and store the mass information. However, the device performance and fabrication process of these semiconductor devices, which are based on a planar transistor, are approaching the physical and technical limits. In order to overcome the limit of conventional MOSFET, many studies on various structures and process techniques have been investigated. According to the International Technology Roadmap for Semiconductors, the next generation cell structure of logic devices such as CMOS and MPU, DRAM, and 3D NAND flash memory is nanowire-type with a gate all around (GAA) structure. A surrounding gate can provide the best possible electrostatic control of the channel region, so the NWFET is the ultimate device structure in terms of gate controllability and short channel immunity. Many studies on NWFET utilizing a GAA structure fabricated by the top-down and bottom-up methods and 3D NAND flash memory with a GAA structure have been advanced. However, Systematic studies on the carrier transport mechanisms and the electrical characteristics in theses semiconductor devices utilizing a GAA structure are less. This study was performed to theoretically investigate the carrier transport mechanisms and the electrical characteristics in semiconductor devices utilizing a GAA structure to understand the physical phenomena and improve the device performance. In chapter 2, electronic structures of semiconductor quantum nanowires is investigated to understand the physical phenomena and the quantum effect in 1-DEG channel of GAA MOSFET. Strain distributions, carrier distributions, and electronic subband energies for quantum nanowires at several temperatures are numerically calculated by using a FDM with and without taking into account shape-based strain effects. The experimental (E1-HH1) interband transitions for quantum nanowires, as determined from the temperature- and structure- dependent PL spectra, are in reasonable agreement with the theoretical (E1-HH1) transitions. In chapter 3, the dependence of the electrical properties on the diameter of the Si nanowire and on the doping concentrations of the Si bulk and the Si nanowires for the GAA TSNWFETs fabricated by the top-down method is investigated to understand their device characteristics and obtain the device optimization. The electrical characteristics of the GAA TSNWFETs and the FETs without Si nanowires are simulated by using the three-dimensional TCAD simulation tools of Sentaurus and taking into account quantum effects. While the switching and the short-channel immunity characteristics, such as the SS, the current drivability per cross-sectional area, and the DIBL for the TSNWFETs, increase with decreasing nanowire diameter, the threshold voltage and the total on-current for the TSNWFETs decrease, resulting in a deterioration of device performances like the sensing speed and margin. When the off-state leakage current is slightly changed within 1 × 10-13 A, the total on-current of the TSNWFETs with an optimized boron concentration is 23.3 μA and is increased by 37% in comparison with that of the as-fabricated TSNWFETs. The current density, the conduction band edge, and the potential profiles in the TSNWFETs clarify the dominant current paths and carrier transport properties. While the threshold voltage of the TSNWFETs linearly increases with increasing nanowire boron concentration, their SS and the DIBL remain almost constant. In chapter 4, the electrical characteristics of the NWFET with Schottky contacts fabricated by the bottom-up method are investigated by using a circuit simulation. A compact model of the current-voltage relation for the NWFET taking into account dependence of the electrical properties on the diameter and the concentration of the Si nanowire of the NWFET with a metal-semiconductor Schottky contact has been proposed. The I-V characteristics of the NWFET are analytically calculated by using a quantum drift-diffusion current transport model taking into accout an equivalent circuit together with the quantum effect of the Si nanowires and a Schottky model at Schottky barriers. The material parameters dependent on different diameters and concentrations of the Si nanowire were numerically estimated from the physical properties of the Si nanowire. The threshold voltage, the mobility, and the doping density of the Si nanowire and the Schottky barrier height at a metal-Si nanowire heterointerface in the NWFET were estimated by using the theoretical model. The simulated results of the Si NWFET are resonable agreement with those of experimental data within a 5% error. In chapter 5, the electrical properties and optimization trap distribution in the charge trap layer of 3D NAND flash memory devices are investigated to improve the retention characteristics and the device reliabilities of 3D NAND flash memory devices. The programming and retention characteristics for CTF memory devices are theoretically simulated by using the model taking into account Shockley-Reed statistics, the continuity equation, and the Pöisson equation. The simulation results show that the dominant tunneling mechanism during the programming operation in the CTF memory devices is varied from the FN tunneling to the DT processes and from the DT to the modified FN tunneling processes due to the decrease of the electric field generated in the tunneling oxide layer resulting from the increase of the injected carriers in the charge trap layer. The trap distribution in the silicon-nitride layer, which is estimated by using experimental results, is used to clarify the retention characteristics of CTF memory devices. Simulation results show that the retention characteristics in CTF memory devices increase with increasing trap density near and above the Fermi-level in the charge trap layer.