Effective Test Pattern Compression Technique for System-on-a-Chip Test

Abstract

n recent years, the semiconductor industry has emerged and DFT (Design-for-Testability) of SoC (System-on-a-Chip) is essential in order to reduce the test time and cost. Typical DFT techniques are BIST (Built-in-Self-Test) and scan test. These techniques ensure the SoC reliability through high fault coverage; however, due to ATE memory area to store the test data, significant cost is generated. To reduce this cost, test data compression techniques are proposed. Typical test compression technology, Huffman, Golomb, there is such as FDR (Frequency-directed run-length) algorithm. In this paper, in the test compression technology, the compression ratio is to use the kind of high FDR algorithm. The FDR type, there is a EFDR to improve the compression rate than the existing FDR (Extended-FDR) and SAFDR (Shifted-Alternate-FDR). In this paper, the proposed Frequency-ordered system shows FDR, EFDR, the improvement of significant compression rate is allowed to apply to SAFDR. Using this technique, the compression ratio can be maximized, and so can result in significantly reducing the overall production test costs and time.