A Study of Physical Parameter Analysis Program/Erase Speed and Reliability of 3D NAND Flash Cells with Gate-All-Around Structure

Abstract

Three-dimensional (3D) NAND flash memory architecture has been found to be the most critical solution to the floating-gate (FG) memory for terabit memory density in nonvolatile memory (NVM) devices. In particular, the gate-all-around (GAA) charge trap flash (CTF) memory with a vertical nanowire channel is considered to be one of the most promising architectures in future 3D NAND flash technologies, allowing a lower program/erase operation voltage, a simpler fabrication process, and higher scaling capability and reliability performance than conventional floating-gate flash memory devices. It successful application to NVM devices with memory cell characteristics was reported. Furthermore, owing to the reduction of corner and fringing field effects during program and erase operations, GAA-CTF memory devices allow more uniform trapped charge distribution in the charge-trapping layer, a lower program/erase operation voltage, stress-induced leakage current (SILC) immunity and markedly reduced capacitive coupling between adjacent cells with respect to the FG memory. However, Memory devices with O/N/O (SiO2/SiN/SiO2) cells have the inherent problems of a low erase speed and the data retention characteristics of the CTF memory devices at high temperatures have inherent problems owing to the retention charge loss in the charge trapping layer. Thus, as the modeling and simulation of memory cells with ONO structure are required to practical understand the electrical and reliability characteristics in terms of the physical properties of silicon nitride layer. Here, we confirmed the program/erase speed and reliability of three-dimensional (3D) gate-all-around (GAA) metal–oxide–SiNX–oxide–silicon (MONOS) flash cells by TCAD simulation to improve the problems mentioned above. First, we present an investigation of the program and erase speed characteristics of 3D GAA-MONOS flash cells. The effect of the tunneling oxide layer thickness in 3D GAA MONOS cells has been experimentally investigated and studied by 3D technology computer-aided design (TCAD) simulation. In particular, we considered physical parameters such as trap density, capture cross section, and trap level in order to analyze the physical properties of the silicon nitride layer. Simulation results indicated that the trap density significantly affects the program efficiency compared with other physical parameters, and the trap level mainly affects the erase efficiency. From these simulation results, we confirmed from the experimental results that the modeling accuracy is about 80%. Moreover, the simulation results for the program and erase speeds of the GAA MONOS flash cells were in reasonable agreement with experimental results. Second, we present an investigation of the retention characteristics of 3D GAA-MONOS flash cells. The effect of retention charge loss in 3D GAA-MONOS flash cells at elevated temperatures has been experimented and studied by technology computer-aided design (TCAD) simulation. In particular, we considered the dependence of the trap energy level in nitride material on the retention characteristics of the 3D GAA-MONOS flash cells by TCAD simulation. Here, simulation results showed that acceptor trap energy level considerably affects the retention charge loss compared with donor trap energy level in the silicon nitride layer that has a Gaussian trap distribution. Moreover, as the acceptor trap energy level becomes shallower, the effect on retention charge loss increases with increasing temperature. From these results, we confirmed that the simulation results for the retention characteristics of 3D GAA-MONOS flash cells were in reasonable agreement with the experimental results.