초저전압 0.4-V 델타-시그마 모듈레이터 연구
- Title
- 초저전압 0.4-V 델타-시그마 모듈레이터 연구
- Other Titles
- Research on Ultra Low-Voltage 0.4-V Delta-Sigma Modulators
- Author
- 윤영현
- Alternative Author(s)
- Younghyun Yoon
- Advisor(s)
- 노정진
- Issue Date
- 2016-08
- Publisher
- 한양대학교 일반대학원
- Degree
- Doctor
- Abstract
- This dissertation presents delta-sigma modulators that operates at extremely low supply voltage of 0.4 V without using a clock boosting technique. A mixed differential difference amplifier (DDA) integrator and a hybrid switching integrator are proposed. To maintain the advantages of a discrete-time integrator in oversampled data converters, the mixed DDA integrator is developed that removes the input sampling switch in a switched-capacitor integrator. Conventionally, many low-voltage delta-sigma modulators have used high-voltage generating circuits to boost the clock voltage levels. The mixed DDA integrator with both a switched-resistor and a switched-capacitor technique is developed to implement a discrete-time integrator without clock boosted switches. The proposed mixed DDA integrator is demonstrated by a third-order delta-sigma modulator with a feedforward topology. The fabricated modulator shows a 68-dB signal-to-noise-plus-distortion ratio (SNDR) for 20-kHz signal bandwidth with an oversampling ratio of 80. The chip consumes 140 μWof power at a true 0.4-V power supply, which is the lowest voltage without a clock boosting technique among the state-of-the-art modulators in this signal band.
The proposed hybrid switching integrator consists of both switched-resistor and switched-capacitor operations and significantly reduces distortion at a low supply voltage. Variation in the turn-on resistance, which is the main source of distortion, is avoided by placing the switches at the virtual ground node of the amplifier. The proposed low-voltage design scheme can replace commonly-used clock boosting techniques, which rely on internal high-voltage generation circuits. A fabricated modulator achieves a 76.1-dB SNDR and an 82-dB dynamic range (DR) at a 20-kHz bandwidth. The measured total power consumption is 63 μW from a 0.4-V supply voltage. The measured results show robust SNDR performance, even at ±10% supply voltage variations. The measured results also show stable performance over a wide temperature range.
- URI
- https://repository.hanyang.ac.kr/handle/20.500.11754/125596http://hanyang.dcollection.net/common/orgView/200000487144
- Appears in Collections:
- GRADUATE SCHOOL[S](대학원) > ELECTRONIC COMMUNICATION ENGINEERING(전자통신공학과) > Theses (Ph.D.)
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