New methods for the improvement of reliability and test efficiency of 3D SIC

Abstract

Despite of development of complementary metal-oxide semiconductor (CMOS) fabrication technology, even the size of transistor is smaller, the exponentially increasing size of system design according to Moore’s law has introduced larger size of semiconductor device. However, the trend of semiconductor devices is a smaller foam factor. Therefore, three-dimensional stacked integrated circuit (3D-SIC) structure that stacks two-dimensional (2D) semiconductors has been proposed. 3D-SIC enables the integration of heterogeneous fabrication processes on the same chip. But heat from stacked dies is more serious than 2D, and it affects the aging of semiconductor devices, as a result, it may cause critical system failure. In this dissertation, new methods have been proposed for improving reliability and test efficiency of 3D-SIC. First, an efficient test method for detecting through silicon via (TSV) defects during pre-bond test stage has been proposed. The pre-bond test stage is most important for yield among 3D-SIC test stages. Defects of TSV have been analyzed for pre-bond test stage, and IEEE Std. 1500 wrapper cells have been modified for detecting those defects. Experimental results show its functionality and stability. Second, estimating aging level of CMOS circuit has been proposed. Under higher temperature, CMOS circuit becomes aged and delays signal transmission because of many temperature related reasons such as negative/positive bias temperature instability, hot carrier injection and time dependent dielectric breakdown. Estimating aging level method has been proposed under operating environment, and its applications for improving reliability and performance have been described also. In addition, its power consumption is minimized by constraining its work during normal operation, and experiments have been conducted to verify the effectiveness of power consumption management. Third, techniques for improving the performance of error correcting code (ECC) have been proposed. Similar as CMOS circuit, retention errors can occur easier in memories under higher temperature. It may change stored data in memory. The changed data can be detected and corrected by ECC decoder. The proposed methods for improving performance of ECC for NAND flash memory are described in details and experimented.