Fully Programmable Redundancy Circuits for STT-MRAM
- Title
- Fully Programmable Redundancy Circuits for STT-MRAM
- Author
- 박상규
- Keywords
- Terms-Magnetic tunnel junction (MTJ); redundancy circuit; spin-transfer-torque magnetic random access memory (STT-MRAM); yield enhancement
- Issue Date
- 2017-10
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Citation
- IEEE TRANSACTIONS ON MAGNETICS, v. 53, no. 10, Article no. 3400706
- Abstract
- We propose fully programmable redundancy schemes for spin-transfer-torque magnetic random access memories (STT-MRAMs). To store redundancy information, these schemes use magnetic tunnel junctions (MTJs), which are core memory elements of STT-MRAMs. This can greatly simplify the fabrication process of STT-MRAMs. Furthermore, it also allows reprogramming of the redundancy information after packaging or even during normal use by end-users without requiring any special high-voltage setup. We propose two redundancy schemes. First, we propose an address comparator, which uses MTJs and is a direct replacement of a conventional address comparator. Second, we propose a scheme in which the redundancy circuits share the storage cells and read-write peripheral circuits with the normal data array structure.
- URI
- https://ieeexplore.ieee.org/document/7968323https://repository.hanyang.ac.kr/handle/20.500.11754/115960
- ISSN
- 0018-9464; 1941-0069
- DOI
- 10.1109/TMAG.2017.2723476
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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