Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박상규 | - |
dc.date.accessioned | 2019-12-01T15:06:04Z | - |
dc.date.available | 2019-12-01T15:06:04Z | - |
dc.date.issued | 2017-10 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON MAGNETICS, v. 53, no. 10, Article no. 3400706 | en_US |
dc.identifier.issn | 0018-9464 | - |
dc.identifier.issn | 1941-0069 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/7968323 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/115960 | - |
dc.description.abstract | We propose fully programmable redundancy schemes for spin-transfer-torque magnetic random access memories (STT-MRAMs). To store redundancy information, these schemes use magnetic tunnel junctions (MTJs), which are core memory elements of STT-MRAMs. This can greatly simplify the fabrication process of STT-MRAMs. Furthermore, it also allows reprogramming of the redundancy information after packaging or even during normal use by end-users without requiring any special high-voltage setup. We propose two redundancy schemes. First, we propose an address comparator, which uses MTJs and is a direct replacement of a conventional address comparator. Second, we propose a scheme in which the redundancy circuits share the storage cells and read-write peripheral circuits with the normal data array structure. | en_US |
dc.description.sponsorship | This work was supported by the Future Semiconductor Device Technology Development Program funded by Ministry of Trade, Industry and Energy and Korea Semiconductor Research Consortium under Grant 10044608. The CAD tools used in this work was supported by IDEC, South Korea. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | en_US |
dc.subject | Terms-Magnetic tunnel junction (MTJ) | en_US |
dc.subject | redundancy circuit | en_US |
dc.subject | spin-transfer-torque magnetic random access memory (STT-MRAM) | en_US |
dc.subject | yield enhancement | en_US |
dc.title | Fully Programmable Redundancy Circuits for STT-MRAM | en_US |
dc.type | Article | en_US |
dc.relation.no | 10 | - |
dc.relation.volume | 53 | - |
dc.identifier.doi | 10.1109/TMAG.2017.2723476 | - |
dc.relation.page | 1-6 | - |
dc.relation.journal | IEEE TRANSACTIONS ON MAGNETICS | - |
dc.contributor.googleauthor | Lee, Dong-Gi | - |
dc.contributor.googleauthor | Park, Sang-Gyu | - |
dc.relation.code | 2017003573 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | sanggyu | - |
dc.identifier.orcid | http://orcid.org/0000-0002-6051-0163 | - |
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