Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 김태환 | - |
dc.date.accessioned | 2019-11-26T05:32:09Z | - |
dc.date.available | 2019-11-26T05:32:09Z | - |
dc.date.issued | 2017-06 | - |
dc.identifier.citation | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, v. 17, no. 6, page. 4173-4175 | en_US |
dc.identifier.issn | 1533-4880 | - |
dc.identifier.issn | 1533-4899 | - |
dc.identifier.uri | https://www.ingentaconnect.com/content/asp/jnn/2017/00000017/00000006/art00086 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/114596 | - |
dc.description.abstract | The vertical NAND flash memory devices with asymmetric string structure were introduced in order to reduce the word-line interference, and their electric characteristics were investigated as functions of the asymmetric factor (AF) by using technology computer-aided design (TCAD) sentaurus simulation tool. The difference in the threshold voltage (V-th) shift of the target cell was decreased with increasing AF; it was 0.435 x 10(-3) V at AF of 0 nm, and 0.009 x 10(-3) V at AF of 40 nm. This reduction of the word-line interference for vertical NAND flash memory devices with an increased AF was explained by the increased average distance between the target cell and the three closest cells located at the adjacent string. | en_US |
dc.description.sponsorship | This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2016R1A2A1A05005502), and this research was partially supported by Samsung Electronics Co. | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | AMER SCIENTIFIC PUBLISHERS | en_US |
dc.subject | Vertical NAND Flash Memory | en_US |
dc.subject | Word-Line Interference | en_US |
dc.subject | Poly-Silicon Channel | en_US |
dc.subject | Charge Trapping Layer | en_US |
dc.subject | Threshold Voltage Shift | en_US |
dc.title | Effects of Asymmetric String Structure on Word-Line Interference in the Vertical NAND Flash Memory Devices | en_US |
dc.type | Article | en_US |
dc.relation.no | 6 | - |
dc.relation.volume | 17 | - |
dc.identifier.doi | 10.1166/jnn.2017.13425 | - |
dc.relation.page | 4173-4175 | - |
dc.relation.journal | JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY | - |
dc.contributor.googleauthor | Lee, Jun Gyu | - |
dc.contributor.googleauthor | Yoo, Keon-Ho | - |
dc.contributor.googleauthor | Kim, Tae Whan | - |
dc.relation.code | 2017011537 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | twk | - |
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