A New Low Leakage Design Method by Efficient Searching Techniques

Abstract

Due to increased integration density and reduced threshold voltages, leakage current reduction becomes important in the CMOS design for low power consumption. In a CMOS combinational logic circuit, the leakage current in the standby state depends on the state of the inputs.

In this paper we present New Input Vector Control(NIVC) algorithm for minimal leakage power. This algorithm finds the Minimal Leakage Ventor(MLV)and MLV reduces leakage current up to 22.01% on the average for TSMC 0.18um process parameters. MLV has proven to be very useful in reducing leakage currents in standby mode of operating.

Keywords : power consumption, leakage current, minimum leakage input ventor