A Study on Macro-model and Robust Sensing Scheme for Next-generation Resistive Memory (STT-MRAM and PRAM)

Abstract

STT-MRAM and PRAM are ones of the most promising candidates for the next-generation non-volatile memory to replace DRAM and FLASH memories. They show strong advantages in performance, such as non-volatility, high speed, low power consumption and high density [1-5]. STT-MRAM and PRAM structure contains storage devices called Magnetic Tunnel Junction (MTJ) and Phase Change Material (PCM) device between the bit-line (BL) and source-line (SL). MTJ consists of thin tunneling oxide barrier, such as MgO layer, between pinned ferromagnetic layer (PL) and free (switching) magnetic layer (FL). The resistance of MTJ depends on the magnetization parallelism state between PL and FL, which shows low resistance (RP) and high resistance (RAP) with parallel magnetization and anti-parallel magnetization, respectively. The magnetization of MTJ switches according to the current direction when current larger than critical current (ICri) is applied to the cell. The resistance difference between RP and RAP is called Tunneling Magneto-Resistance (TMR) ratio [6,7]. PCM consists of chalcogenide materials, such as GeSbTe and CrGeTe, which changes the crystallization states, which is crystalline and amorphous, according to the cell temperature generated by Joule-heating when pulse is applied. When SET pulse is applied the cell, PCM shows low resistance with the crystalline state, and when RESET pulse is applied to the cell, high resistance with amorphous states. STT-MRAM and PRAM is non-volatile resistive memory which stores and determine the data using the resistance difference. Recently, many researchers on STT-MRAM and PRAM sensing circuits have been proposed. Self-reference schemes are proposed for the STT-MRAM [15-23] and various sensing schemes to enhance the sense margin and read endurance of PRAM has been proposed [45-56]. However, self-reference sensing schemes requires relatively long read-access time since they need to perform read and write operation twice, and conventional sensing schemes for STT-MRAM and PRAM requires an accurate reference standards to compare and determine current resistance states of MTJ and PCM considering the resistance variation due to process and environmental conditions. The resistance of MTJ has dependent characteristics on parameters such as oxide thickness (tox), surface (A), temperature (T), and bias voltage (Vb) [8-14]. Also, the resistance of PCM has dependent characteristic on the composition ratio between materials and volume (V) variation during the fabrication process. Variation of such parameters of the storing device could cause serious resistance variation, which could lead read failure. While designing STT-MRAM or PRAM sensing circuits, resistance variation from such parameter variations should be considered, in order to reduce the read failure and enhance the reliability of the memory device. Therefore, an accurate macro-model for MTJ and PCM, which is compatible with Hspice simulation, should be developed. There have been many researches on macro-model of MTJ [57-62] and PCM [63-70] for the circuit simulation. However, most of the models used fixed value and applied variation for the resistance of such devices without considering dependency on various parameters. In this thesis, I proposed MTJ, PCM and OTS macro-models compatible with Hspice simulation using Verilog-A language, based on the electrical characteristic studies from experimental results and previous research works. Then, we propose various sensing schemes which enhances the memory performance of STT-MRAM and PRAM and verify the validity of proposed schemes by simulation using proposed macro-models.