Simulated Annealing을 이용한 FPGA 배치에서의 cooling 계획

Abstract

In this paper, we propose a new cooling schedule for placement of Field Programmable Gate Array (FPGA) by using Simulated Annealing. By using the proposed cooling schedule, we obtain improved results, when compared to those of Versatile Place and Route (VPR). Experiment results shows that cost and move number were reduced by 0.3%, 22.8% respectively.