A Single-ended Simultaneous Bidirectional Transceiver in 65-nm CMOS Technology
- Title
- A Single-ended Simultaneous Bidirectional Transceiver in 65-nm CMOS Technology
- Author
- 유창식
- Keywords
- Simultaneous bidirectional transceiver; echo cancellation; blind oversampling; data recovery; CMOS
- Issue Date
- 2016-12
- Publisher
- IEEK PUBLICATION CENTER
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 16, NO 6, Page. 817-824
- Abstract
- A simultaneous bidirectional transceiver over a single wire has been developed in a 65 nm CMOS technology for a command and control bus. The echo signals of the simultaneous bidirectional link are cancelled by controlling the decision level of receiver comparators without power-hungry operational amplifier (op-amp) based circuits. With the clock information embedded in the rising edges of the signals sent from the source side to the sink side, the data is recovered by an open-loop digital circuit with 20 times blind oversampling. The data rate of the simultaneous bidirectional transceiver in each direction is 75 Mbps and therefore the overall signaling bandwidth is 150 Mbps. The measured energy efficiency of the transceiver is 56.7 pJ/b and the bit-error-rate (BER) is less than 10(-12) with 2(7)-1 pseudo-random binary sequence (PRBS) pattern for both signaling directions.
- URI
- http://koreascience.or.kr/article/JAKO201607959403059.pagehttps://repository.hanyang.ac.kr/handle/20.500.11754/102368
- ISSN
- 1598-1657; 2233-4866
- DOI
- 10.5573/JSTS.2016.16.6.817
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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