Thermal aware clock tree optimization with balanced clock skew in 3D ICs

Abstract

Thermal issues are a primary concern in the three-dimensional integrated circuit (3D IC) design. This paper addresses a clock tree synthesis problem under thermal variation for 3D IC designs. Our major contributions are the reduced and balanced skew with minimum wirelength under both nonuniform and uniform thermal conditions. Our proposed clock tree synthesis algorithms search the routing path to find the clock merging point at each level of the clock tree. Experimental results show that our methods significantly reduce and balance clock skew values with the minimum wirelength overhead.