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A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs

Title
A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs
Author
권오경
Keywords
successive approximation register ADC; column parallel readout; CMOS image sensor
Issue Date
2015-11
Publisher
MDPI AG
Citation
SENSORS, v. 16, NO 1, Page. 1-2
Abstract
This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 x 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 m CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 s to 0.45 s and random noise from 848.3 V to 270.4 V, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.
URI
http://www.mdpi.com/1424-8220/16/1/27http://hdl.handle.net/20.500.11754/28754
ISSN
1424-8220
DOI
10.3390/s16010027
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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