Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults
- Title
- Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults
- Author
- 박성주
- Keywords
- Crosstalk faults; interconnect test; static faults; system-on-a-chip (SoC); test pattern
- Issue Date
- 2009-01
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Citation
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v. 56, NO. 1, Page. 56-60
- Abstract
- The effect of crosstalk-induced errors becomes more significant in high-performance circuits and systems. In this paper, compact crosstalk test patterns are introduced for a system-on-a-chip and board level interconnects considering physically effective aggressors. By being able to target multiple victim lines, 6n, where n is the number of nets patterns are drastically reduced to a constant number 6D, where D indicates the effective distance among interconnect nets. The test quality for static and crosstalk faults are completely preserved with 6D patterns.
- URI
- https://ieeexplore.ieee.org/document/4753705https://repository.hanyang.ac.kr/handle/20.500.11754/185664
- ISSN
- 1549-7747;1558-3791
- DOI
- 10.1109/TCSII.2008.2010168
- Appears in Collections:
- COLLEGE OF COMPUTING[E](소프트웨어융합대학) > COMPUTER SCIENCE(소프트웨어학부) > Articles
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