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dc.contributor.author최정욱-
dc.date.accessioned2022-09-21T02:00:15Z-
dc.date.available2022-09-21T02:00:15Z-
dc.date.issued2020-12-
dc.identifier.citationIEEE ACCESS, v. 9, page. 8006-8027en_US
dc.identifier.issn2169-3536en_US
dc.identifier.urihttps://ieeexplore.ieee.org/document/9311614en_US
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/173093-
dc.description.abstractRecently, semantic segmentation based on deep neural network (DNN) has attracted attention as it exhibits high accuracy, and many studies have been conducted on this. However, DNN-based segmentation studies focused mainly on improving accuracy, thus greatly increasing the computational demand and memory footprint of the segmentation network. For this reason, the segmentation network requires a lot of hardware resources and power consumption, and it is difficult to be applied to an environment where they are limited, such as an embedded system. In this paper, we propose a binarized encoder-decoder network (BEDN) and a binarized deconvolution engine (BiDE) accelerating the network to realize lowpower, real-time semantic segmentation. BiDE implements a binarized segmentation network with custom hardware, greatly reducing the hardware resource usage and greatly increasing the throughput of network implementation. The deconvolution used for upsampling in a segmentation network includes zero padding. In order to enable deconvolution in a binarized segmentation network that cannot express zero, we introduce zero-aware binarized deconvolution which skips padded zero activations and zero-aware batch normalization embedded binary activation considering zero-skipped convolution. The BEDN, which is a binarized segmentation network proposed to be accelerated on BiDE, has acceptable accuracy while greatly reducing the computational and memory demands of the segmentation network through full-binarization and simple structure. BEDN has a network size of 0.21 MB, and its maximum memory usage is 1.38 MB. BiDE was implemented on Xilinx ZU7EV field-programmable gate array (FPGA) to operate at 187.5 MHz. BiDE accelerated the proposed BEDN within CamVid11 images of 480×360 size at 25.89 frames per second (FPS) achieving a performance of 1.682 Tera operations per second (TOPS) and 824 Giga operations per second per watt (GOPS/W).en_US
dc.description.sponsorshipThis work was supported in part by the Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Korea Government (MSIT) under Grant 2020-0-01373, in part by the Arti~cial Intelligence Graduate School Program, Hanyang University, and in part by the Research and Development Program, Ministry of Trade, Industry and Energy/Korea Evaluation Institute of Industrial Technology (MOTIE/KEIT), "Developing Processor-Memory-Storage Integrated Architecture for Low Power, High Performance Big Data Servers,'' under Grant 10077609.en_US
dc.language.isoenen_US
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INCen_US
dc.subjectBinarized neural network; binarized deconvolution; binarized segmentation network; zero-aware deconvolution; zero-skip deconvolution; neural network acceleratoren_US
dc.titleBinarized Encoder-Decoder Network and Binarized Deconvolution Engine for Semantic Segmentationen_US
dc.typeArticleen_US
dc.relation.volume9-
dc.identifier.doi10.1109/ACCESS.2020.3048375en_US
dc.relation.page8006-8027-
dc.relation.journalIEEE ACCESS-
dc.contributor.googleauthorKim, Hyunwoo-
dc.contributor.googleauthorKim, Jeonghoon-
dc.contributor.googleauthorChoi, Jungwook-
dc.contributor.googleauthorLee, Jungkeol-
dc.contributor.googleauthorSong, Yong Ho-
dc.relation.code2020045465-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentSCHOOL OF ELECTRONIC ENGINEERING-
dc.identifier.pidchoij-
dc.identifier.orcidhttps://orcid.org/0000-0002-3075-8694-


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