계층적 SoC 테스트 접근을 위한 명령어 기반 코아 연결 모듈의 설계

Abstract

For a Systern—on-a—Ch ip(SoC ) comprised of mu ltip le IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based W rapped Core L ink ing M odu le (W C LM ) tha t enables systematic integration of IE E E 1149.1 T A P 'd cores and P I 500 wrapped cores w ith requiring least amount o f area overhead compared w ith other state—o f—art techniques. The design preserves compatibility w ith standards and scalability for hierarchical access