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계층적 SoC 테스트 접근을 위한 명령어 기반 코아 연결 모듈의 설계

Title
계층적 SoC 테스트 접근을 위한 명령어 기반 코아 연결 모듈의 설계
Other Titles
A Design of Instruction Based Wrapped Core Linking Module for Hierarchical SoC Test Access
Author
박성주
Keywords
경계스캔 설계; IEEE 1149.1; P1500; SoC 테스트; 코아 테스트
Issue Date
2003-03
Publisher
대한전기학회
Citation
전기학회논문지 D. v. 52, no. 3, page. 156-162
Abstract
For a Systern—on-a—Ch ip(SoC ) comprised of mu ltip le IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based W rapped Core L ink ing M odu le (W C LM ) tha t enables systematic integration of IE E E 1149.1 T A P 'd cores and P I 500 wrapped cores w ith requiring least amount o f area overhead compared w ith other state—o f—art techniques. The design preserves compatibility w ith standards and scalability for hierarchical access
URI
http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01261997https://repository.hanyang.ac.kr/handle/20.500.11754/155250
ISSN
1229-6287
Appears in Collections:
COLLEGE OF COMPUTING(소프트웨어융합대학)[E] > COMPUTER SCIENCE(소프트웨어학부) > Articles
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