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dc.contributor.author김희준-
dc.date.accessioned2019-06-18T00:35:22Z-
dc.date.available2019-06-18T00:35:22Z-
dc.date.issued2007-07-
dc.identifier.citation대한전자공학회 2007년 하계종합학술대회, Page. 913 - 914en_US
dc.identifier.urihttp://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01597691&language=ko_KR-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/106706-
dc.description.abstractThis paper presents a new fast locking phase-locked loop. Although the conventional fast phase-locked loop has two tuning loops, a proposed phase-locked loop was realized using just one tuning loop. The proposed circuit was simulated by HSPICE with a standard CMOS 0.25㎛ process parameter.en_US
dc.language.isoko_KRen_US
dc.publisher대한전자공학회en_US
dc.title새로운 듀얼 슬로프 위상 주파수 검출기를 이용한 위상고정 시간이 빠른 위상고정 루프en_US
dc.title.alternativeA Fast Locking Phase-Locked Loop using a New Dual-Slope Phase Frequency Detectoren_US
dc.typeArticleen_US
dc.contributor.googleauthor박종하-
dc.contributor.googleauthor임정현-
dc.contributor.googleauthor김훈-
dc.contributor.googleauthor김희준-
dc.sector.campusE-
dc.sector.daehakCOLLEGE OF ENGINEERING SCIENCES[E]-
dc.sector.departmentDIVISION OF ELECTRICAL ENGINEERING-
dc.identifier.pidhjkim-
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COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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