김희준
2019-06-18T00:35:22Z
2019-06-18T00:35:22Z
2007-07
대한전자공학회 2007년 하계종합학술대회, Page. 913 - 914
http://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE01597691&language=ko_KR
https://repository.hanyang.ac.kr/handle/20.500.11754/106706
This paper presents a new fast locking phase-locked loop. Although the conventional fast phase-locked loop has two tuning loops, a proposed phase-locked loop was realized using just one tuning loop. The proposed circuit was simulated by HSPICE with a standard CMOS 0.25㎛ process parameter.
ko_KR
대한전자공학회
새로운 듀얼 슬로프 위상 주파수 검출기를 이용한 위상고정 시간이 빠른 위상고정 루프
A Fast Locking Phase-Locked Loop using a New Dual-Slope Phase Frequency Detector
Article
박종하
임정현
김훈
김희준
E
COLLEGE OF ENGINEERING SCIENCES[E]
DIVISION OF ELECTRICAL ENGINEERING
hjkim