Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression
- Title
- Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression
- Author
- 박성주
- Keywords
- Test data compression; code-based test data compression; scan chain reordering; low power testing; routing congestion; TEST DATA VOLUME; RUN-LENGTH CODE; CHIP; RELAXATION; TIME
- Issue Date
- 2016-10
- Publisher
- 대한전자공학회
- Citation
- JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 16, No. 5, Page. 582-594
- Abstract
- Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead.
- URI
- http://www.dbpia.co.kr/Journal/ArticleDetail/NODE07041140https://repository.hanyang.ac.kr/handle/20.500.11754/102845
- ISSN
- 1598-1657
- DOI
- 10.5573/JSTS.2016.16.5.582
- Appears in Collections:
- COLLEGE OF COMPUTING[E](소프트웨어융합대학) > COMPUTER SCIENCE(소프트웨어학부) > Articles
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