Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 박성주 | - |
dc.date.accessioned | 2019-04-29T01:54:48Z | - |
dc.date.available | 2019-04-29T01:54:48Z | - |
dc.date.issued | 2016-10 | - |
dc.identifier.citation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 16, No. 5, Page. 582-594 | en_US |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.uri | http://www.dbpia.co.kr/Journal/ArticleDetail/NODE07041140 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/102845 | - |
dc.description.abstract | Various test data compression techniques have been developed to reduce the test costs of system-on-a-chips. In this paper, a scan chain reordering algorithm for code-based test data compression techniques is proposed. Scan cells within an acceptable relocation distance are ranked to reduce the number of conflicts in all test patterns and rearranged by a positioning algorithm to minimize the routing overhead. The proposed method is demonstrated on ISCAS '89 benchmark circuits with their physical layout by using a 180 nm CMOS process library. Significant improvements are observed in compression ratio and test power consumption with minor routing overhead. | en_US |
dc.description.sponsorship | This research was partly supported by the MOTIE(Ministry of Trade, Industry & Energy (10052875)) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device and the National Research Foundation of Korea (NRF) grant (MEST) (No. NRF-2013R1A1A2059326). | en_US |
dc.language.iso | en_US | en_US |
dc.publisher | 대한전자공학회 | en_US |
dc.subject | Test data compression | en_US |
dc.subject | code-based test data compression | en_US |
dc.subject | scan chain reordering | en_US |
dc.subject | low power testing | en_US |
dc.subject | routing congestion | en_US |
dc.subject | TEST DATA VOLUME | en_US |
dc.subject | RUN-LENGTH CODE | en_US |
dc.subject | CHIP | en_US |
dc.subject | RELAXATION | en_US |
dc.subject | TIME | en_US |
dc.title | Low Power Scan Chain Reordering Method with Limited Routing Congestion for Code-based Test Data Compression | en_US |
dc.type | Article | en_US |
dc.relation.no | 5 | - |
dc.relation.volume | 16 | - |
dc.identifier.doi | 10.5573/JSTS.2016.16.5.582 | - |
dc.relation.page | 582-594 | - |
dc.relation.journal | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.contributor.googleauthor | Kim, DY | - |
dc.contributor.googleauthor | Ansari, MA | - |
dc.contributor.googleauthor | Jung, JH | - |
dc.contributor.googleauthor | Park, SJ | - |
dc.relation.code | 2016010716 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF COMPUTING[E] | - |
dc.sector.department | DIVISION OF COMPUTER SCIENCE | - |
dc.identifier.pid | paksj | - |
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