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dc.contributor.author김동규-
dc.date.accessioned2019-01-07T01:38:26Z-
dc.date.available2019-01-07T01:38:26Z-
dc.date.issued2016-10-
dc.identifier.citationJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 16, NO. 5, Page. 564-581en_US
dc.identifier.issn1598-1657-
dc.identifier.issn2233-4866-
dc.identifier.urihttp://www.dbpia.co.kr/Journal/ArticleDetail/NODE07041139-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/81083-
dc.description.abstractWe present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively.en_US
dc.description.sponsorshipThis work was supported by the research fund of Signal Intelligence Research Center supervised by Defense Acquisition Program Administration and Agency for Defense Development of Korea and by the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2016-H8501-16-1008) supervised by the IITP (Institute for Information & communications Technology Promotion).en_US
dc.language.isoenen_US
dc.publisherIEEK PUBLICATION CENTERen_US
dc.subjectPerformance analysisen_US
dc.subjectdigital integrated circuitsen_US
dc.subjectprime numberen_US
dc.subjectpublic key cryptosystemen_US
dc.subjectinformation securityen_US
dc.titleDesign and Analysis of Efficient Parallel Hardware Prime Generatorsen_US
dc.typeArticleen_US
dc.relation.no5-
dc.relation.volume16-
dc.identifier.doi10.5573/JSTS.2016.16.5.564-
dc.relation.page564-581-
dc.relation.journalJOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE-
dc.contributor.googleauthorKim, Dong Kyue-
dc.contributor.googleauthorChoi, Piljoo-
dc.contributor.googleauthorLee, Mun-Kyu-
dc.contributor.googleauthorPark, Heejin-
dc.relation.code2016010716-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.piddqkim-
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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