Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 김동규 | - |
dc.date.accessioned | 2019-01-07T01:38:26Z | - |
dc.date.available | 2019-01-07T01:38:26Z | - |
dc.date.issued | 2016-10 | - |
dc.identifier.citation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v. 16, NO. 5, Page. 564-581 | en_US |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.issn | 2233-4866 | - |
dc.identifier.uri | http://www.dbpia.co.kr/Journal/ArticleDetail/NODE07041139 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/81083 | - |
dc.description.abstract | We present an efficient hardware prime generator that generates a prime p by combining trial division and Fermat test in parallel. Since the execution time of this parallel combination is greatly influenced by the number k of the smallest odd primes used in the trial division, it is important to determine the optimal k to create the fastest parallel combination. We present probabilistic analysis to determine the optimal k and to estimate the expected running time for the parallel combination. Our analysis is conducted in two stages. First, we roughly narrow the range of optimal k by using the expected values for the random variables used in the analysis. Second, we precisely determine the optimal k by using the exact probability distribution of the random variables. Our experiments show that the optimal k and the expected running time determined by our analysis are precise and accurate. Furthermore, we generalize our analysis and propose a guideline for a designer of a hardware prime generator to determine the optimal k by simply calculating the ratio of M to D, where M and D are the measured running times of a modular multiplication and an integer division, respectively. | en_US |
dc.description.sponsorship | This work was supported by the research fund of Signal Intelligence Research Center supervised by Defense Acquisition Program Administration and Agency for Defense Development of Korea and by the MSIP (Ministry of Science, ICT and Future Planning), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2016-H8501-16-1008) supervised by the IITP (Institute for Information & communications Technology Promotion). | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEK PUBLICATION CENTER | en_US |
dc.subject | Performance analysis | en_US |
dc.subject | digital integrated circuits | en_US |
dc.subject | prime number | en_US |
dc.subject | public key cryptosystem | en_US |
dc.subject | information security | en_US |
dc.title | Design and Analysis of Efficient Parallel Hardware Prime Generators | en_US |
dc.type | Article | en_US |
dc.relation.no | 5 | - |
dc.relation.volume | 16 | - |
dc.identifier.doi | 10.5573/JSTS.2016.16.5.564 | - |
dc.relation.page | 564-581 | - |
dc.relation.journal | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.contributor.googleauthor | Kim, Dong Kyue | - |
dc.contributor.googleauthor | Choi, Piljoo | - |
dc.contributor.googleauthor | Lee, Mun-Kyu | - |
dc.contributor.googleauthor | Park, Heejin | - |
dc.relation.code | 2016010716 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | dqkim | - |
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