Executing Synchronous Dataflow Graphs on an SPM based Multi-core Architecture
- Title
- Executing Synchronous Dataflow Graphs on an SPM based Multi-core Architecture
- Author
- 오현옥
- Keywords
- Components, Circuits, Devices and Systems; Communication, Networking and Broadcast Technologies; Computing and Processing; Prefetching; Multicore processing; Schedules; Delay; Tiles; prefetching; Multiprocessor scheduling; synchronous dataflow; scratch pad memory; multicore architecture; memory overlay
- Issue Date
- 2012-06
- Publisher
- IEEE
- Citation
- DAC Design Automation Conference 2012, 2012, P.664-671
- Abstract
- In this paper we are concerned about executing synchronous dataflow (SDF) applications on a multicore architecture where a core has a limited size of scratchpad memory (SPM). Unlike traditional multi-processor scheduling of SDF graphs, we consider the SPM size limitation that incurs code and data overlay overhead. Since the scheduling problem is intractable, we propose an EA(evolutionary algorithm)-based technique. To hide memory latency, prefetching is aggressively performed in the proposed technique. The experimental results show that our approach reduces the overlay overhead significantly compared to a non-optimized approach and the previous approach.
- URI
- https://ieeexplore.ieee.org/document/6241577/http://hdl.handle.net/20.500.11754/67347
- ISSN
- 0738-100X
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > INFORMATION SYSTEMS(정보시스템학과) > Articles
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