Timing driven global router with a pin partition method for 3D stacked integrated circuits

Abstract

Three-dimensional (3D) integration technology packs together multiple active device dies, achieving a higher level of integration within a given footprint. However, due to an increase in the design volume and complexity, routing has become a challenging problem in 3D IC designs. In this paper, we propose a timing driven routing algorithm for 3D IC with a load balancing method that distributes the capacitance of the interconnections including TSV. In the load balancing step, the sink pins are partitioned to balance the loads within the routing tree. The routing trees are then created by merging the sub-trees that are generated with the balanced group.