Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 유창식 | - |
dc.date.accessioned | 2018-04-02T02:14:56Z | - |
dc.date.available | 2018-04-02T02:14:56Z | - |
dc.date.issued | 2014-06 | - |
dc.identifier.citation | IEICE ELECTRONICS EXPRESS, 11(11), 20140351p | en_US |
dc.identifier.issn | 1349-2543 | - |
dc.identifier.uri | http://www.jstage.jst.go.jp/article/elex/11/11/11_11.20140351/_article/-char/en | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11754/54731 | - |
dc.description.abstract | A clock and data recovery (CDR) circuit for 1.5-5.0 Gb/s wireline transceiver is described. A phase locked loop (PLL) with dual phase frequency detector (PFD) and charge pump (CP) pairs performs the seamless phase rotation for the CDR circuit to track the phase and frequency difference. The CDR circuit implemented in a 65 nm CMOS process consumes 22.8 mW from a 1.2 V supply at 5.0 Gb/s. For 25 MHz jitter frequency, the CDR circuit can tolerate up to 0.21 unit-interval (UI) jitter with bit error rate (BER) smaller than 10(-12). | en_US |
dc.description.sponsorship | This work is sponsored by IT R&D program MKE/KEIT (No. 10035202, Large Scale hyper-MLC SSD Technology Development) and the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIP) (No. 2013R1A2A2A01004958). The CAD tools were provided by IC Design Education Center (IDEC), KAIST, Korea. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG, KIKAI-SHINKO-KAIKAN BLDG, 3-5-8, SHIBA-KOEN, MINATO-KU, TOKYO, 105-0011, JAPAN | en_US |
dc.subject | clock and data recovery (CDR) | en_US |
dc.subject | wireline transceiver | en_US |
dc.subject | phase locked loop (PLL) | en_US |
dc.subject | phase rotation | en_US |
dc.subject | CMOS | en_US |
dc.title | A 1.5-5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop | en_US |
dc.title.alternative | s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop | en_US |
dc.type | Article | en_US |
dc.relation.no | 11 | - |
dc.relation.volume | 11 | - |
dc.identifier.doi | 10.1587/elex.11.20140351 | - |
dc.relation.page | 0-0 | - |
dc.relation.journal | IEICE ELECTRONICS EXPRESS | - |
dc.contributor.googleauthor | Choi, Dong-Ho | - |
dc.contributor.googleauthor | Yoo, Chang-sik | - |
dc.relation.code | 2014030895 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | csyoo | - |
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