ON-STATE DARIN CURRENT MODELING FOR GRAIN AND GRAIN BOUNDARY EFFECT OF THE POLYSILICON MATERIALS AT VARIOUS TEMPERATURES

Abstract

We present analytical on-state drain current model of 2-dimensional (2D) planar-type poly-Silicon TFT devices. The effect of grain and grain boundary on the carrier transport of 2D poly-Silicon devices has been studied by simulation (matlab) tool. Especially, we considered physical parameters such as grain length (Lg), grain boundary length (Lgb) and grain boundary trap density (NGB) in order to analyze cell performance of the poly-Silicon materials at various temperature. Thus, we simulated the temperature dependence of the on-state drain current within a wide temperature range from 248 K (-25 °C) to 348 K (75 °C). From these results, we confirmed that grain length and grain boundary trap density significantly effects on-state drain current in poly-Silicon materials.