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COLLEGE OF ENGINEERING SCIENCES[E](공학대학)
ELECTRICAL ENGINEERING(전자공학부)
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Results 1-7 of 7 (Search time: 0.002 seconds).
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Issue Date
Title
Author(s)
2017-07
BPPT–Bulk Potential Protection Technique for Hardened Sequentials
백상현
2016-11
An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology
백상현
2017-01
Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs
백상현
2017-04
Soft error study on DDR4 SDRAMs using a 480 MeV proton beam
백상현
2015-04
An SEU-Tolerant DICE Latch Design With Feedback Transistors
백상현
2015-04
Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams
백상현
2013-04
Memory Reliability Analysis for Multiple Block Effect of Soft Errors
백상현
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soft error
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radiation hardening
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logic upset cluster
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single event effect
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stacked structure
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Charge sharing
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CMOS TECHNOLOGY
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DDR3 SDRAM
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DDR4 SDRAM
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dual interlocked storage cell (DICE)
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