An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology
- Title
- An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology
- Author
- 백상현
- Keywords
- FDSOI; flip-flop; radiation hardening; single event effect; single event upset; soft error; stacked structure; SINGLE-EVENT UPSET; CMOS TECHNOLOGY; SOFT; MITIGATION; IMPACT; SRAMS
- Issue Date
- 2016-11
- Publisher
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- Citation
- IEEE TRANSACTIONS ON NUCLEAR SCIENCE, v. 63, No. 6, Page. 3003-3009
- Abstract
- In this paper, we present D flip-flop, Quatro, and stacked Quarto flip-flop designs fabricated in a commercial 28-nm CMOS FDSOI technology. Stacked-transistor structures are introduced in the stacked Quatro design to protect the sensitive devices of the original structure. Striking either of the stacked devices will not upset the latch because the conduction path to the supply rail is still cut off by the other off-state device. The irradiation experimental results substantiate that the stacked Quatro design has significantly better SEU tolerance (e.g., higher heavy ion upset Linear Energy Transfer threshold and smaller cross-section data) than the reference designs. It introduces power and area penalties because the proposed design duplicates and stacks two sensitive PMOS devices. Additionally, the impact of technology scaling on Quatro in various technology nodes (130-nm, 65-nm, and 40-nm) has been studied suggesting decreasing upset threshold and decreasing cross-section data.
- URI
- https://ieeexplore.ieee.org/abstract/document/7740104/https://repository.hanyang.ac.kr/handle/20.500.11754/71299
- ISSN
- 0018-9499; 1558-1578
- DOI
- 10.1109/TNS.2016.2627003
- Appears in Collections:
- COLLEGE OF ENGINEERING SCIENCES[E](공학대학) > ELECTRICAL ENGINEERING(전자공학부) > Articles
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