Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 유창식 | - |
dc.date.accessioned | 2018-03-20T05:09:31Z | - |
dc.date.available | 2018-03-20T05:09:31Z | - |
dc.date.issued | 2014-12 | - |
dc.identifier.citation | Integrated Circuits (ISIC), 2014, P.79-82 | en_US |
dc.identifier.issn | 2325-0631 | - |
dc.identifier.uri | http://ieeexplore.ieee.org/document/7029467/ | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11754/49492 | - |
dc.description.abstract | A digital phase locked loop (DPLL) has been developed in which the phase detection is performed by a bangbang phase detector (BBPD). By dithering the offset of the BBPD, its phase detection gain can be made to be constant and independent of the reference clock jitter. Therefore the bandwidth of the DPLL can be kept constant regardless of the magnitude of the reference clock jitter. The DPLL with the offset dithered BBPD has been implemented in a 65-nm CMOS process and occupies only 0.098-mm 2 . The measurement results show the offset dithering of the BBPD has negligible effect on the period jitter of the DPLL output clock. | en_US |
dc.description.sponsorship | This work was supported by SK-Hynix Semiconductor Inc. Korea and the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIP) (No.2013R1A2A2A01004958). The CAD tools and chip implementation service were provided by IDEC, KAIST, Korea. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | Phase locked loop (PLL) | en_US |
dc.subject | digital PLL (DPLL) | en_US |
dc.subject | bang-bang phase detector (BBPD) | en_US |
dc.subject | jitter | en_US |
dc.subject | dithering | en_US |
dc.subject | sigma-delta | en_US |
dc.subject | modulator | en_US |
dc.title | Digital Phase Locked Loop (DPLL) with Offset Dithered Bang-Bang Phase Detector (BBPD) for Bandwidth Control | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/ISICIR.2014.7029467 | - |
dc.relation.page | 101-104 | - |
dc.contributor.googleauthor | Yoo, Changsik | - |
dc.contributor.googleauthor | Kim, Younghoon | - |
dc.contributor.googleauthor | Jeon, Min-Ki | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | csyoo | - |
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