Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 정정화 | - |
dc.date.accessioned | 2018-03-16T00:23:53Z | - |
dc.date.available | 2018-03-16T00:23:53Z | - |
dc.date.issued | 2014-08 | - |
dc.identifier.citation | ETRI Journal, 2014, 36(4), p643-653 | en_US |
dc.identifier.issn | 1225-6463 | - |
dc.identifier.uri | http://onlinelibrary.wiley.com/doi/10.4218/etrij.14.0113.1233/abstract | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11754/47555 | - |
dc.description.abstract | To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively. | en_US |
dc.description.sponsorship | This research was supported by the MSIP (Ministry of Science, ICT & Future Planning), Korea, under the ITRC (Information Technology Research Center) support program supervised by the NIPA (National IT Industry Promotion Agency) (NIPA-2013-H0301-13-1011). | en_US |
dc.language.iso | en | en_US |
dc.publisher | ELECTRONICS TELECOMMUNICATIONS RESEARCH INST, 161 KAJONG-DONG, YUSONG-GU, TAEJON 305-350, SOUTH KOREA | en_US |
dc.subject | Three-dimensional integrated circuit | en_US |
dc.subject | power delivery network | en_US |
dc.subject | through-silicon via | en_US |
dc.title | Voltage Optimization of Power Delivery Networks through Power Bump and TSV Placement in 3D ICs | en_US |
dc.type | Article | en_US |
dc.relation.volume | 36 | - |
dc.identifier.doi | 10.4218/etrij.14.0113.1233 | - |
dc.relation.page | 642-652 | - |
dc.relation.journal | ETRI JOURNAL | - |
dc.contributor.googleauthor | Jang, Cheol-Jon | - |
dc.contributor.googleauthor | Chong, Jong-wha | - |
dc.relation.code | 2014029126 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DEPARTMENT OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | jchong | - |
dc.identifier.researcherID | 7102639995 | - |
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