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Hiding rollback latency in log-based eager hardware transactional memory

Title
Hiding rollback latency in log-based eager hardware transactional memory
Author
이인환
Keywords
Hardware transactional memory; Multi-processing; Stanford; Benchmarking; Storage allocation (computer); Hardware
Issue Date
2014-01
Publisher
INST ENGINEERING TECHNOLOGY-IET, MICHAEL FARADAY HOUSE SIX HILLS WAY STEVENAGE, HERTFORD SG1 2AY, ENGLAND
Citation
Electronics Letters, 16 January 2014, Vol 50, No 2, p.72-74
Abstract
The use of a rollback buffer (RB) for hiding the rollback latency in logbased eager hardware transactional memory is proposed. The RB allows a transaction to abort without performing rollback, but still makes the transaction's old values immediately available. In effect, the rollback latency almost disappears. When running the Stanford transactional applications for multi-processing benchmark on a 16-core processor that implements the LogTM-SE, the speedup (decrease in execution time) achieved with a 2 KB RB is 15.8% on average. ⓒ The Institution of Engineering and Technology 2014.
URI
http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6729316http://hdl.handle.net/20.500.11754/47484
ISSN
0013-5194; 1350-911X
DOI
10.1049/el.2013.3133
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > COMPUTER SCIENCE(컴퓨터소프트웨어학부) > Articles
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