Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 최창환 | - |
dc.date.accessioned | 2018-03-15T08:57:33Z | - |
dc.date.available | 2018-03-15T08:57:33Z | - |
dc.date.issued | 2012-01 | - |
dc.identifier.citation | MICROELECTRONIC ENGINEERING, Jan 2012, 89, P.34-36, 3P. | en_US |
dc.identifier.issn | 0167-9317 | - |
dc.identifier.uri | https://www.sciencedirect.com/science/article/abs/pii/S0167931711000451 | - |
dc.identifier.uri | http://hdl.handle.net/20.500.11754/47458 | - |
dc.description.abstract | We investigated controllability and scalability of flatband voltage (V-FB) and equivalent oxide thickness (EOT) using various thin capping films such as single layers (Hf, La, Ti, Al, Ta) and mixed layers (Hf/Ti, Al/Ti, Ta/Ti) with high-k gate dielectric/metal gate stack for gate-first process. With increasing thickness, negative V-FB shift observed with Hf and La while Ti and Al provided positive shift in conjunction with EOT scaling down to 0.6 nm simultaneously. Ti-based mixed cap layers showed both positive V-FB shift and EOT scaling with increasing thickness and higher Ti ratio. Al cap exhibited turn-around effect in V-FB shift behaviors beyond 0.7 nm thickness, which is attributed to strong scavenging interfacial layer rather than dipole formation. Based on V-FB modulation and EOT scaling, we propose novel process integration scheme for the gate first CMOS by adjusting Al composition in TiAlN single metal gate. (C) 2011 Elsevier B.V. All rights reserved. | en_US |
dc.description.sponsorship | This work was supported by the research fund of Hanyang University(HY-2010-00000000300). | en_US |
dc.language.iso | en | en_US |
dc.publisher | ELSEVIER SCIENCE BV | en_US |
dc.subject | Work-function | en_US |
dc.subject | High-k gate dielectric | en_US |
dc.subject | Metal gate | en_US |
dc.subject | EOT scaling | en_US |
dc.subject | CMOS integration | en_US |
dc.title | Thickness and material dependence of capping layers on flatband voltage (V-FB) and equivalent oxide thickness (EOT) with high-k gate dielectric/metal gate stack for gate-first process applications | en_US |
dc.title.alternative | metal gate stack for gate-first process applications | en_US |
dc.type | Article | en_US |
dc.relation.volume | 89 | - |
dc.identifier.doi | 10.1016/j.mee.2011.01.034 | - |
dc.relation.page | 34-36 | - |
dc.relation.journal | MICROELECTRONIC ENGINEERING | - |
dc.contributor.googleauthor | Choi, Chang-hwan | - |
dc.relation.code | 2012206695 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DIVISION OF MATERIALS SCIENCE AND ENGINEERING | - |
dc.identifier.pid | cchoi | - |
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