Implementation of parallel lattice reduction-aided MIMO detector using graphics processing unit
- Title
- Implementation of parallel lattice reduction-aided MIMO detector using graphics processing unit
- Author
- 최승원
- Keywords
- Lattice reduction; GPU; LR-aided detection; SYSTEM
- Issue Date
- 2012-11
- Publisher
- SPRINGER, VAN GODEWIJCKSTRAAT 30, 3311 GZ DORDRECHT, NETHERLANDS
- Citation
- Analog Integrated Circuits and Signal Processing, Vol.73 No.2 [2012], 559-567
- Abstract
- Since H. Yao proposed the lattice reduction (LR)-aided detection algorithm for the MIMO detector, one can exploit the diversity gain provided by the LR method to achieve performance comparable to the maximum likelihood (ML) algorithm but with complexity close to the simple linear detection algorithms such as zero forcing (ZF), minimum mean squared error, and successive interference cancellation, etc. In this paper, in order to reduce the processing time of the LR-aided detector, a graphics processing unit (GPU) has been proposed as the main modem processor in such a way that the detections can be performed in parallel using multiple threads in the GPU. A 2X2 multiple input multiple output (MIMO) WiMAX system has been implemented using a GPU to verify that various MIMO detection algorithms such as ZF, ML, and LR-aided methods can be processed in real-time. From the experimental results, we show that GPUs can realize a 2X2 WiMAX MIMO system adopting an LR-aided detector in real-time. We achieve a processing time of 2.75 ms which meets the downlink duration specification of 3 ms. BER performance of experimental tests also indicates that the LR-aided MIMO detector can fully exploit diversity gain as well as ML detector.
- URI
- https://link.springer.com/article/10.1007%2Fs10470-012-9870-3http://hdl.handle.net/20.500.11754/43595
- ISSN
- 0925-1030; 1573-1979
- DOI
- 10.1007/s10470-012-9870-3
- Appears in Collections:
- COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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