Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 김영현 | - |
dc.date.accessioned | 2024-04-22T23:51:12Z | - |
dc.date.available | 2024-04-22T23:51:12Z | - |
dc.date.issued | 2023-04-26 | - |
dc.identifier.citation | 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM) | en_US |
dc.identifier.uri | https://information.hanyang.ac.kr/#/eds/detail?an=edseee.10103116&dbId=edseee | en_US |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/189934 | - |
dc.description.abstract | Over the years, there has been much research on ferroelectric field-effect transistors (FeFETs) for memory applications. In this work, we propose a novel recessed channel FeFET with gate metalferroelectric (FE)-metal-FE-metal-SiO2 interlayer (IL)-silicon (MFMFMIS) gate stack, which is named a dual ferroelectric recessed channel FeFET (DFRFeFET) aimed to increase the memory window (MW) for high-performance memory applications. With calibrated FE parameters and device models in technology computer-aided design (TCAD) simulation, we found that the DF-RFeFET can have a large MW of 3.2 V. In addition, guidelines for the DF-RFeFET design are provided in terms of the thickness ratio of the inner and outer FE layers to maximize the MW | en_US |
dc.description.sponsorship | This research was supported by the Technology Innovation Program (20015909) through the Korea Evaluation Institute of Industrial Technology (KEIT), funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea), Korea Basic Science Institute (National Research Facilities and Equipment Center) grant funded by the Ministry of Education (2021R1A6C101A405), and the IC Design Education Center (IDEC), Korea. | en_US |
dc.language | en_US | en_US |
dc.publisher | IEEE | en_US |
dc.relation.ispartofseries | ;1-3 | - |
dc.subject | FeFET | en_US |
dc.subject | MFMFMIS | en_US |
dc.subject | ferroelectric recessed channel | en_US |
dc.title | Simulation of a Recessed Channel Ferroelectric-Gate Field-Effect Transistor with a Dual Ferroelectric Gate Stack for Memory Application | en_US |
dc.type | Article | en_US |
dc.identifier.doi | 10.1109/EDTM55494.2023.10103116 | en_US |
dc.relation.page | 1-3 | - |
dc.contributor.googleauthor | Chen, Simin | - |
dc.contributor.googleauthor | Ahn, Dae-Hwan | - |
dc.contributor.googleauthor | Ui An, Seong | - |
dc.contributor.googleauthor | Kim, Younghyun | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF SCIENCE AND CONVERGENCE TECHNOLOGY[E] | - |
dc.sector.department | DEPARTMENT OF PHOTONICS AND NANOELECTRONICS | - |
dc.identifier.pid | younghyunkim | - |
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