Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 김병호 | - |
dc.date.accessioned | 2024-04-11T02:09:13Z | - |
dc.date.available | 2024-04-11T02:09:13Z | - |
dc.date.issued | 2024-02-13 | - |
dc.identifier.citation | ELECTRONICS | en_US |
dc.identifier.issn | 2079-9292 | en_US |
dc.identifier.uri | https://information.hanyang.ac.kr/#/eds/detail?an=001168362700001&dbId=edswsc | en_US |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/189686 | - |
dc.description | The EDA tool was supported by the IC Design Education Center (IDEC), Korea. | en_US |
dc.description.abstract | The capacitor mismatch among diverse defects caused by variations in the manufacturing process significantly affects the linearity of the capacitor array used to implement the capacitive digital-to-analog converter (CDAC) in the successive-approximation register (SAR) analog-to-digital converter (ADC). Accordingly, the linearity of the SAR ADC is limited by that of capacitor array, resulting in serious yield loss. This paper proposes an efficient foreground self-calibration technique to enhance the linearity of the SAR ADCs by mitigating the capacitor mismatch based on the split ADC architecture along with variable capacitors. In this work, two ADC channels (i.e., ADC1 and ADC2) for the split ADC architecture include their capacitive DACs (CDACs) whose binary-weighted capacitor arrays consist of variable capacitors. A charge-sharing SAR ADC is used for each ADC channel. In the normal operation mode, their digital outputs are averaged to be the final ADC output, as in a conventional split ADC. In the calibration mode, every single binary-weighted capacitor for the two ADCs is sequentially calibrated by making parallel or/and antiparallel connection among two or thee capacitors from the two channels. For instance, because the capacitors of the CDACs ideally exhibit the binary-weighted relation as Cn=2xCn-1, the variable capacitor Cn of ADC1 can be updated to be closest to the sum of Cn-1 of ADC1 and Cn-1 of ADC2 for the calibration. For the process, the two capacitor arrays of the two ADCs can be reconfigured to be connected to each other, so that the Cn of ADC1 can be connected with two of the Cn-1 of ADC1 and ADC2 in antiparallel. The two voltages at the top and the bottom plates of the CDAC are compared by a comparator of ADC1, and the comparison results are used to update Cn. This process is iterated, until Cn is in agreement with the sum of two of Cn-1. Finally, all the capacitors can be calibrated in this way to have the binary-weighted relation. The simulation results based on the proposed work with a split SAR ADC model verified that the proposed technique can be practically used, by showing that the total harmonic distortion and the signal-to-noise-and-distortion ratio were enhanced by 21.8 dB and 6.4 dB, respectively. | en_US |
dc.description.sponsorship | This research was supported in part by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education (No. 2016R1D1A1B020 13884). This research was also supported in part by Korea Institute for Advancement of Technology (KIAT) grant funded by the Korea Government (MOTIE) (P0012451, The Competency Development Program for Industry Specialist). This research was also supported in part by the MOTIE (Ministry of Trade, Industry and Energy) (1415180306) and KSRC (Korea Semiconductor Research Consortium) (20019164) support program for the development of the future semiconductor device, and the research fund of Hanyang University (HY-2017-N). | en_US |
dc.language | en_US | en_US |
dc.publisher | MDPI | en_US |
dc.relation.ispartofseries | v. 13, NO 4;755-774 | - |
dc.subject | self-testing | en_US |
dc.subject | alternative testing | en_US |
dc.subject | mixed-signal testing | en_US |
dc.subject | manufacturing test | en_US |
dc.subject | production test | en_US |
dc.subject | built-in self-test (BIST) | en_US |
dc.subject | self-calibration | en_US |
dc.subject | self-healing | en_US |
dc.subject | analog-to-digital converter (ADC) | en_US |
dc.title | A Tunable Foreground Self-Calibration Scheme for Split Successive-Approximation Register Analog-to-Digital Converter | en_US |
dc.type | Article | en_US |
dc.relation.no | 4 | - |
dc.relation.volume | 13 | - |
dc.identifier.doi | 10.3390/electronics13040755 | en_US |
dc.relation.page | 755-774 | - |
dc.relation.journal | ELECTRONICS | - |
dc.contributor.googleauthor | Park, Joonsung | - |
dc.contributor.googleauthor | Lee, Jiwon | - |
dc.contributor.googleauthor | Abraham, Jacob A. | - |
dc.contributor.googleauthor | Kim, Byoungho | - |
dc.relation.code | 2024008579 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF ENGINEERING SCIENCES[E] | - |
dc.sector.department | SCHOOL OF ELECTRICAL ENGINEERING | - |
dc.identifier.pid | brandonkim | - |
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