Efficient use of unused spare columns to improve memory error correcting rate
- Title
- Efficient use of unused spare columns to improve memory error correcting rate
- Author
- 박성주
- Keywords
- logic sharing; Memory ECC; misscorrection probability; parity check matrix; SEC-DED
- Issue Date
- 2011-11
- Publisher
- IEEEv
- Citation
- Proceedings of the Asian Test Symposium, article no. 6114752, Page. 335-340
- Abstract
- In the deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. Spare columns are often included in memories to repair defective cells or bit lines during production test. In many cases, the repair process will not use all spare columns. Schemes have been proposed to exploit these unused spare columns to store additional check bits which can be used to reduce the miscorrection probability for triple errors in single error correction - double error detection (SEC-DED). These additional check bits increase the dimensions of the parity check matrix (H-matrix) requiring extra area and delay overhead. A method is proposed in this paper to efficiently fill the extra rows of the H-matrix on the basis of similarity of logic between the other rows. Optimization of the whole H-matrix is accomplished through logic sharing within a feasible operating time resulting in the reduced area and delay overhead. © 2011 IEEE.
- URI
- https://ieeexplore.ieee.org/document/6114752/https://repository.hanyang.ac.kr/handle/20.500.11754/185653
- ISSN
- 1081-7735
- DOI
- 10.1109/ATS.2011.28
- Appears in Collections:
- COLLEGE OF COMPUTING[E](소프트웨어융합대학) > COMPUTER SCIENCE(소프트웨어학부) > Articles
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