Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 심종인 | - |
dc.date.accessioned | 2023-07-21T02:38:04Z | - |
dc.date.available | 2023-07-21T02:38:04Z | - |
dc.date.issued | 2001-06 | - |
dc.identifier.citation | IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v. 9, NO. 3, Page. 450-460 | - |
dc.identifier.issn | 1063-8210;1557-9999 | - |
dc.identifier.uri | https://ieeexplore.ieee.org/document/929579 | en_US |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/184084 | - |
dc.description.abstract | A new fast and accurate capacitance determination methodology for intricate multilayer VLSI interconnects is presented, Since a multilayer interconnect structure is too complicated to be directly tractable, it is simplified by investigating charge distributions within the system, The quasi-three-dimensional (3-D) capacitances of the structure are then determined by combining a set of solid-ground-based two-dimensional (2-D) capacitances and shielding effects that can be independently calculated from the simplified structure, The shielding effects due to the neighboring lines of a line can be analytically determined from the given layout dimensions, The solid-ground-based 2-D capacitances can also be quickly computed from the simplified structure. Thus, the proposed capacitance determination methodology is much more cost-efficient than conventional 3-D-based methods. It is shown that the calculated quasi-3-D capacitances have excellent agreement with 3-D held-solver-based results within 5% error. | - |
dc.description.sponsorship | Manuscript received September 14, 1999; revised July 28, 2000. This work was supported by the Center for Electronic Packaging Materials, Korea Science and Engineering Foundation. | - |
dc.language | en | - |
dc.publisher | Institute of Electrical and Electronics Engineers | - |
dc.subject | crosstalk | - |
dc.subject | interconnect capacitance | - |
dc.subject | multilayer | - |
dc.subject | shielding effect | - |
dc.subject | signal delay | - |
dc.subject | VLSI interconnects | - |
dc.title | Fast and accurate quasi-three-dimensional capacitance determination of multilayer VLSI interconnects | - |
dc.type | Article | - |
dc.relation.no | 3 | - |
dc.relation.volume | 9 | - |
dc.identifier.doi | 10.1109/92.929579 | - |
dc.relation.page | 450-460 | - |
dc.relation.journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems | - |
dc.contributor.googleauthor | Jin, Woojin | - |
dc.contributor.googleauthor | Eo, Yungseon | - |
dc.contributor.googleauthor | Eisenstadt, WR | - |
dc.contributor.googleauthor | Shim, Jong In | - |
dc.sector.campus | E | - |
dc.sector.daehak | 과학기술융합대학 | - |
dc.sector.department | 나노광전자학과 | - |
dc.identifier.pid | jishim | - |
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