효과적인 자가보정 기반의 Flash 아날로그-디지털 컨버터

Abstract

This research proposes efficient histograms-based foreground calibrations by analyzing the effects of the imperfect resistor string and nonlinear comparators on the ADC decision levels, where those are caused by the variations of the fabrication process for the flash analog-to-digital converter (ADC). For our first proposed calibration method, the linearity errors are calibrated using offset variable comparator based on the correlation between integral nonlinearity (INL) and errors at the flash ADC decision levels. In addition, the best-fit analysis during the calibration process facilitates the accurate design of the offset-adjustable comparators. For our second proposed calibration method, the calibration process time is significantly reduced, using the symmetrical behavior of the nonlinearity in the resistor string used for the structure of a fully differential flash ADC. The simulations are performed with the behavioral model of an 8-bit flash ADC, to verify the performance of the foreground self-calibrations proposed. For the simulation results, the differential nonlinearity (DNL) and the INL were enhanced from 1.42 LSB to 0.18 LSB and from 2.31 LSB to 0.12 LSB, respectively. In particular, the signal-to-noise ratio (SNR), the total harmonic distortion (THD), and the signal-to-noise-and-distortion (SINAD) have shown to be improved by 2.06 dB, 12.88 dB, and 7.88 dB.