Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 한재덕 | - |
dc.date.accessioned | 2022-10-13T04:20:05Z | - |
dc.date.available | 2022-10-13T04:20:05Z | - |
dc.date.issued | 2021-01 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v. 68, no. 3, page. 1012-1022 | en_US |
dc.identifier.issn | 1549-8328; 1558-0806 | en_US |
dc.identifier.uri | https://ieeexplore.ieee.org/document/9314047 | en_US |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/175339 | - |
dc.description.abstract | LAYout with Gridded Objects (LAYGO), a Python-based layout-generation engine for enhancing the design productivity of custom circuit layouts in advanced CMOS processes, is presented and verified by implementing a time-interleaved SAR (TI-SAR) ADC instance in a 16 nm CMOS FinFET technology. LAYGO supports rapid generation by placing customized templates on process-specific placement grids, thereby encapsulating the design rules and process-specific structures. The templates can be located based on their relative positional information, which further enhances the description capability and portability. Interconnecting wires are routed on the grids for design rule abstractions, with additional customizations and support for multi-patterning. The functions for the on-grid placement and routing use advanced indexing and slicing with multi-dimensional object containers to improve the description and parameterization capabilities. Multiple TI-SAR ADC layouts are generated using LAYGO in 28-16 nm CMOS technologies. One instance is fabricated in a 16 nm CMOS FinFET process and measured, achieving a 38.2 dB signal-to-noise-and-distortion ratio (SNDR) at 7 GS/s after digital calibration and consuming 45.2 mW. Owing to its high customization capability, the design achieved the highest sampling rate (7 GS/s) among the generated ADCs. | en_US |
dc.description.sponsorship | This work was supported in part by the DARPA CRAFT under Grant HR0011-16-C-0052, in part by the Samsung Research Funding and Incubation Center of Samsung Electronics under Project SRFC-MA1702-01, in part by the Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Korean Government (MSIT), Development of Multi-Rate, Ultra-High-Speed Links with 100-Gbps Aggregate Bandwidth for AI Computing Platforms, under Grant 2020-0-01307, and in part by the Research Fund of Hanyang University under Grant HY-2019. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | en_US |
dc.subject | Analog-to-digital converters; layout; design automations | en_US |
dc.title | LAYGO: A Template-and-Grid-Based Layout Generation Engine for Advanced CMOS Technologies | en_US |
dc.type | Article | en_US |
dc.relation.no | 3 | - |
dc.relation.volume | 68 | - |
dc.identifier.doi | 10.1109/TCSI.2020.3046524 | en_US |
dc.relation.page | 1045-1054 | - |
dc.relation.journal | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.contributor.googleauthor | Han, Jaeduk | - |
dc.contributor.googleauthor | Bae, Woorham | - |
dc.contributor.googleauthor | Chang, Eric | - |
dc.contributor.googleauthor | Wang, Zhongkai | - |
dc.contributor.googleauthor | Nikolic, Borivoje | - |
dc.contributor.googleauthor | Alon, Elad | - |
dc.relation.code | 2021004858 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | SCHOOL OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | jdhan | - |
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