Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 유창식 | - |
dc.date.accessioned | 2021-11-01T04:53:28Z | - |
dc.date.available | 2021-11-01T04:53:28Z | - |
dc.date.issued | 2020-04 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v. 56, no. 9, page. 431-432 | en_US |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.issn | 1350-911X | - |
dc.identifier.uri | https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/el.2019.3863 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/166090 | - |
dc.description.abstract | A voltage-mode pulse-amplitude modulation 4 (PAM4) driver with differential ternary R-2R DAC architecture is described. The differential ternary R-2R DAC provides three voltage levels with one R-2R branch, whereas the conventional one provides only two. Therefore, much less R-2R branches are required for a given number of output voltage levels. One of the three voltage levels is realised by simply short circuiting a differential input pair, saving power consumption. Implemented in 65 nm CMOS technology, the voltage-mode PAM4 driver occupies 0.073 mm(2) active silicon area and consumes 1.97 mW/Gbit/s from 1.0 V supply at 10 Gbit/s. | en_US |
dc.description.sponsorship | A part of this work was supported by the Future Interconnect Technology Cluster Programme of Samsung Electronics, South Korea and by the Ministry of Trade, Industry and Energy, South Korea, through the Industrial Technology Innovation Program (IP Development and Standard Definition for 8K/4K Display) under Grant no. 10080285. The CAD tools were provided by the IC Design Education Centre (IDEC), South Korea. | en_US |
dc.language.iso | en | en_US |
dc.publisher | INST ENGINEERING TECHNOLOGY-IET | en_US |
dc.subject | low-power electronics | en_US |
dc.subject | driver circuits | en_US |
dc.subject | CMOS integrated circuits | en_US |
dc.subject | pulse amplitude modulation | en_US |
dc.subject | digital-analogue conversion | en_US |
dc.subject | voltage-mode PAM4 driver | en_US |
dc.subject | voltage-mode pulse-amplitude modulation 4 driver | en_US |
dc.subject | output voltage levels | en_US |
dc.subject | differential input pair | en_US |
dc.subject | 2 active silicon area | en_US |
dc.subject | differential ternary R-2R DAC architecture | en_US |
dc.subject | R-2R branch | en_US |
dc.subject | power consumption | en_US |
dc.subject | CMOS technology | en_US |
dc.subject | voltage 1 | en_US |
dc.subject | 0 V | en_US |
dc.subject | bit rate 10 | en_US |
dc.subject | 0 Gbit | en_US |
dc.subject | s | en_US |
dc.subject | size 65 | en_US |
dc.subject | 0 nm | en_US |
dc.title | Voltage-mode PAM4 driver with differential ternary R-2R DAC architecture | en_US |
dc.type | Article | en_US |
dc.relation.no | 9 | - |
dc.relation.volume | 56 | - |
dc.identifier.doi | 10.1049/el.2019.3863 | - |
dc.relation.page | 431-431 | - |
dc.relation.journal | ELECTRONICS LETTERS | - |
dc.contributor.googleauthor | Lim, B. | - |
dc.contributor.googleauthor | Kim, D. | - |
dc.contributor.googleauthor | Yoo, C. | - |
dc.relation.code | 2020053148 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | SCHOOL OF ELECTRONIC ENGINEERING | - |
dc.identifier.pid | csyoo | - |
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