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dc.contributor.author유창식-
dc.date.accessioned2021-11-01T04:53:28Z-
dc.date.available2021-11-01T04:53:28Z-
dc.date.issued2020-04-
dc.identifier.citationELECTRONICS LETTERS, v. 56, no. 9, page. 431-432en_US
dc.identifier.issn0013-5194-
dc.identifier.issn1350-911X-
dc.identifier.urihttps://ietresearch.onlinelibrary.wiley.com/doi/10.1049/el.2019.3863-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/166090-
dc.description.abstractA voltage-mode pulse-amplitude modulation 4 (PAM4) driver with differential ternary R-2R DAC architecture is described. The differential ternary R-2R DAC provides three voltage levels with one R-2R branch, whereas the conventional one provides only two. Therefore, much less R-2R branches are required for a given number of output voltage levels. One of the three voltage levels is realised by simply short circuiting a differential input pair, saving power consumption. Implemented in 65 nm CMOS technology, the voltage-mode PAM4 driver occupies 0.073 mm(2) active silicon area and consumes 1.97 mW/Gbit/s from 1.0 V supply at 10 Gbit/s.en_US
dc.description.sponsorshipA part of this work was supported by the Future Interconnect Technology Cluster Programme of Samsung Electronics, South Korea and by the Ministry of Trade, Industry and Energy, South Korea, through the Industrial Technology Innovation Program (IP Development and Standard Definition for 8K/4K Display) under Grant no. 10080285. The CAD tools were provided by the IC Design Education Centre (IDEC), South Korea.en_US
dc.language.isoenen_US
dc.publisherINST ENGINEERING TECHNOLOGY-IETen_US
dc.subjectlow-power electronicsen_US
dc.subjectdriver circuitsen_US
dc.subjectCMOS integrated circuitsen_US
dc.subjectpulse amplitude modulationen_US
dc.subjectdigital-analogue conversionen_US
dc.subjectvoltage-mode PAM4 driveren_US
dc.subjectvoltage-mode pulse-amplitude modulation 4 driveren_US
dc.subjectoutput voltage levelsen_US
dc.subjectdifferential input pairen_US
dc.subject2 active silicon areaen_US
dc.subjectdifferential ternary R-2R DAC architectureen_US
dc.subjectR-2R branchen_US
dc.subjectpower consumptionen_US
dc.subjectCMOS technologyen_US
dc.subjectvoltage 1en_US
dc.subject0 Ven_US
dc.subjectbit rate 10en_US
dc.subject0 Gbiten_US
dc.subjectsen_US
dc.subjectsize 65en_US
dc.subject0 nmen_US
dc.titleVoltage-mode PAM4 driver with differential ternary R-2R DAC architectureen_US
dc.typeArticleen_US
dc.relation.no9-
dc.relation.volume56-
dc.identifier.doi10.1049/el.2019.3863-
dc.relation.page431-431-
dc.relation.journalELECTRONICS LETTERS-
dc.contributor.googleauthorLim, B.-
dc.contributor.googleauthorKim, D.-
dc.contributor.googleauthorYoo, C.-
dc.relation.code2020053148-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentSCHOOL OF ELECTRONIC ENGINEERING-
dc.identifier.pidcsyoo-
Appears in Collections:
COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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