A 2-tap switched capacitor FFE transmitter achieving 1-20 Gb/s at 0.72-0.62 pJ/bit

Abstract

This paper presents a 28nm CMOS 1-20Gb/s energy proportional transmitter with 2-tap DDR SC FFE, 64:2 1-latch MUX serialization, rapid-on/off LC OSC, and adjustable clock divider. Switched Capacitor frontend allows for fully dynamic operation for minimal quiescent current consumption. Fast startup time is achieved through the 1-latch based MUX SER along with the on/off LC OSC and the adjustable clock divider. The transmitter operates from 1-20Gb/s, occupies 0.19mm 2 , and consumes 0.72-0.62 pJ/bit.