Histogram기반 자가보정 SAR 아날로그-디지털 컨버터

Abstract

Capacitor mismatches in a capacitive digital-to-analog converter (CDAC) degrade the linearity of a successive-approximation-register (SAR) analog-to-digital converter (ADC) in manufacturing process. This paper proposes a foreground calibration technique to efficiently calibrate the capacitor mismatches of CDAC using an additional variable capacitor based on the correlation analytically derived between capacitances of CDAC and the histogram results from the final ADC outputs. The simulation results verified the linearity enhancement, i.e., 0.75LSB of the differential non-linearity for SAR ADC using the proposed calibration technique.