Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 김병호 | - |
dc.date.accessioned | 2021-09-09T05:25:11Z | - |
dc.date.available | 2021-09-09T05:25:11Z | - |
dc.date.issued | 2020-11 | - |
dc.identifier.citation | 2020년도 대한전자공학회 추계학술대회 논문집, Page. 45-48 | en_US |
dc.identifier.uri | https://www.dbpia.co.kr/journal/articleDetail?nodeId=NODE10521687 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/165093 | - |
dc.description.abstract | Capacitor mismatches in a capacitive digital-to-analog converter (CDAC) degrade the linearity of a successive-approximation-register (SAR) analog-to-digital converter (ADC) in manufacturing process. This paper proposes a foreground calibration technique to efficiently calibrate the capacitor mismatches of CDAC using an additional variable capacitor based on the correlation analytically derived between capacitances of CDAC and the histogram results from the final ADC outputs. The simulation results verified the linearity enhancement, i.e., 0.75LSB of the differential non-linearity for SAR ADC using the proposed calibration technique. | en_US |
dc.language.iso | ko_KR | en_US |
dc.publisher | 대한전자공학회 | en_US |
dc.title | Histogram기반 자가보정 SAR 아날로그-디지털 컨버터 | en_US |
dc.title.alternative | SAR ADC with Histogram-based Foreground Self-Calibration | en_US |
dc.type | Article | en_US |
dc.relation.page | 45-48 | - |
dc.contributor.googleauthor | 이강희 | - |
dc.contributor.googleauthor | 김병호 | - |
dc.sector.campus | E | - |
dc.sector.daehak | COLLEGE OF ENGINEERING SCIENCES[E] | - |
dc.sector.department | DIVISION OF ELECTRICAL ENGINEERING | - |
dc.identifier.pid | brandonkim | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.