Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | 최창환 | - |
dc.date.accessioned | 2021-03-17T00:52:33Z | - |
dc.date.available | 2021-03-17T00:52:33Z | - |
dc.date.issued | 2020-01 | - |
dc.identifier.citation | ACS APPLIED MATERIALS & INTERFACES, v. 12, no. 6, page. 7372-7380 | en_US |
dc.identifier.issn | 1944-8244 | - |
dc.identifier.issn | 1944-8252 | - |
dc.identifier.uri | https://pubs.acs.org/doi/10.1021/acsami.9b22008 | - |
dc.identifier.uri | https://repository.hanyang.ac.kr/handle/20.500.11754/160612 | - |
dc.description.abstract | Although they have attracted enormous attention in recent years, software-based and two-dimensional hardware-based artificial neural networks (ANNs) may consume a great deal of power. Because there will be numerous data transmissions through a long interconnection for learning, power consumption in the interconnect will be an inevitable problem for low-power computing. Therefore, we suggest and report 3D stackable synaptic transistors for 3D ANNs, which would be the strongest candidate in future computing systems by minimizing power consumption in the interconnection. To overcome the problems of enormous power consumption, it might be necessary to introduce a 3D stackable ANN platform. With this structure, short vertical interconnection can be realized between the top and bottom devices, and the integration density can be significantly increased for integrating numerous neuromorphic devices. In this paper, we suggest and show the feasibility of monolithic 3D integration of synaptic devices using the channel layer transfer method through a wafer bonding technique. Using a low-temperature processible III-V and composite oxide (Al2O3/HfO2/Al2O3)-based weight storage layer, we successfully demonstrated synaptic transistors showing good linearity (alpha(p)/alpha(d) = 1.8/0.5), a high transconductance ratio (6300), and very good stability. High learning accuracy of 97% was obtained in the training of 1 million MNIST images based on the device characteristics. | en_US |
dc.description.sponsorship | This work was partly supported by a National Research Foundation of Korea (NRF) grant funded by the Korean government (MEST) (grant 2016910562, 201902071513, 201902072072, 201901074452), in part by the future Semiconductor Device Technology Development Program (10052962), in part by BK21 plus, and in part by the KAIST startup funding (G04180061), KAIST, Korea. | en_US |
dc.language.iso | en | en_US |
dc.publisher | AMER CHEMICAL SOC | en_US |
dc.subject | neuromorphic | en_US |
dc.subject | monolithic 3D integration | en_US |
dc.subject | artificial neural network | en_US |
dc.subject | III-V | en_US |
dc.subject | synapse | en_US |
dc.title | 3D Stackable Synaptic Transistor for 3D Integrated Artificial Neural Networks | en_US |
dc.type | Article | en_US |
dc.relation.no | 6 | - |
dc.relation.volume | 12 | - |
dc.identifier.doi | 10.1021/acsami.9b22008 | - |
dc.relation.page | 7372-7380 | - |
dc.relation.journal | ACS APPLIED MATERIALS & INTERFACES | - |
dc.contributor.googleauthor | Kim, Seong Kwang | - |
dc.contributor.googleauthor | Jeong, YeonJoo | - |
dc.contributor.googleauthor | Bidenko, Pavlo | - |
dc.contributor.googleauthor | Lim, Hyeong-Rak | - |
dc.contributor.googleauthor | Jeon, Yu-Rim | - |
dc.contributor.googleauthor | Kim, Hansung | - |
dc.contributor.googleauthor | Lee, Yun Jung | - |
dc.contributor.googleauthor | Geum, Dae-Myeong | - |
dc.contributor.googleauthor | Han, JaeHoon | - |
dc.contributor.googleauthor | Choi, Changhwan | - |
dc.relation.code | 2020051325 | - |
dc.sector.campus | S | - |
dc.sector.daehak | COLLEGE OF ENGINEERING[S] | - |
dc.sector.department | DIVISION OF MATERIALS SCIENCE AND ENGINEERING | - |
dc.identifier.pid | cchoi | - |
dc.identifier.orcid | https://orcid.org/0000-0002-8386-3885 | - |
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