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dc.contributor.author정재경-
dc.date.accessioned2021-03-09T05:52:18Z-
dc.date.available2021-03-09T05:52:18Z-
dc.date.issued2019-05-
dc.identifier.citationSID Symposium Digest of Technical Papers, v. 50, no. 1, page. 520-523en_US
dc.identifier.issn2168-0159-
dc.identifier.issn0097-966X-
dc.identifier.urihttps://onlinelibrary.wiley.com/doi/abs/10.1002/sdtp.12971-
dc.identifier.urihttps://repository.hanyang.ac.kr/handle/20.500.11754/160310-
dc.description.abstractIn this paper, the effects of post annealing on the structural, chemical and electrical properties of tantalum (Ta) capped IZTO films were examined for use as the channel in thin‐film transistors (TFTs). The onset crystallization temperature of amorphous IZTO was found to be ≥ 700 °C, which is not suitable for glass or plastic substrate‐based display devices. New crystallization method involving the catalytic Ta capping and subsequent post annealing was proposed for the IZTO material system at a low temperature of 200 °C. The TFTs with Ta‐assisted crystallized IZTO channel exhibited a high field‐effect mobility of 60.3 cm2/Vs, subthreshold swing of 0.20 V/decade, threshold voltage of ‐0.39 V, and Ion/off ratio of ~108, which was superior to the control device without Ta‐assisted crystallization. The reason for this high performance is discussed on basis of the lattice ordering and chemical purification of IZTO channel layer. Existence of two dimensional grain boundary defects as a crystallization of IZTO channel layer was found to hardly affect the charge carrier transport, suggesting that they are electrically inactive.en_US
dc.description.sponsorshipThis research was supported by Samsung Displayen_US
dc.language.isoenen_US
dc.publisherWileyen_US
dc.subjectLow Temperature Annealingen_US
dc.subjectIZTOen_US
dc.subjectThin-Film Transistorsen_US
dc.subjectCrystallizationen_US
dc.subjectMetal Cappingen_US
dc.subjectOxide Semiconductoren_US
dc.titleAchieving High Field‐Effect Mobility Exceeding 60 cm2/Vs in IZTO Transistor via Metal‐Assisted Crystallizationen_US
dc.typeArticleen_US
dc.relation.no1-
dc.relation.volume50-
dc.identifier.doi10.1002/sdtp.12971-
dc.relation.page520-523-
dc.contributor.googleauthorOn, Nuri-
dc.contributor.googleauthorJeong, Jae Kyeong-
dc.sector.campusS-
dc.sector.daehakCOLLEGE OF ENGINEERING[S]-
dc.sector.departmentDEPARTMENT OF ELECTRONIC ENGINEERING-
dc.identifier.pidjkjeong1-
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COLLEGE OF ENGINEERING[S](공과대학) > ELECTRONIC ENGINEERING(융합전자공학부) > Articles
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